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The diff-amp in Figure 11.3 of the text has parameters
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Microelectronics: Circuit Analysis and Design
- QUESTION 3: The diff-amp configuration shown in Figure 11.7 is biased at 3.3 V and -3.3 V. The maximum power dissipation in the entire circuit is to be no more than 1.2 mW when v₁ = v₂ = 0. The available transistors have parameters: ß = 130, VBE(on) = 0.71 V, and VA = 00. Design the circuit to produce the maximum possible differential-mode voltage gain, but such that the common-mode input voltage can be within the range - 0.91 < VCM<0.91 V and the transistors are still biased in the forward-active region. What is the value of Ad? R₁ (kQ) Format: 67.42 Rc (kn) Format 48.55 8m (mA/V) Format: 8.3846 Ad Format: 66.55 V+ R₁ IC₁Rc Ic₂Rc ww 23 1010 24 Figure 11.7 2₂ -0 U₂ ICAarrow_forwardDetermine the DC bias values using DC equivalent circuits (in order of VE, VB, VC)arrow_forwardQUESTION 2: The differential amplifier in Figure P11.4 is biased with a three-transistor current source. The transistor parameters: B = 85 , VBE(on) = 0.7 V, and V= 0. Determine a new value of R1 such that VCE4 = 1.3 V. What are the values of Ic4, Ic2, and I4? Ic4 (mA) Format : 4.2 Ic2 (mA) Format : 8.382 I (mA) Format : 5.576 R1 (kN) Format : 5.969 +5 V 8.5 k2 2 k2 2 kQ Q4 VCE4 Qs Q3 Q2 VCE2 -5 V Figure P11.4 wwarrow_forward
- "It is desirable for the following circuit, assuming the transistors are the same." A) Common fashion gain B) Differential gain mode C) Input resistance network D) CMRR E) What effect does the change in load resistance have on the circuit? Vcc Rc Re Qu, Vi PEE -VEEarrow_forwardQUESTION 6: Consider the circuit of Figure P11.3 with transistor parameters ß= 155 , V4=0, and VBE(on) = 0.66 V. The circuit is biased by V*= 6 V and V = -6 V. Design the circuit such that the Q-point values are Icı = Ic2 = 140 µA, and vo1 =vo2 = 1.2 V for vị = v2 = 0. Format : 98.34 Rc (kN) Format : 47.93 RE (kN) Ici RC RC v02 10a RE Figure P11.3arrow_forwardQUESTION 16: For the transistors in the circuit in Figure 11.32, the circuit parameters V* = 1.8V, V = −1.8V, and IQ = 155 μA. The transistor parameters are: k'n = 100 µA/V², k'p = 40 µA/V², VĨN = 0.3V, Vpp = −0.3V, (W/L)n = 8, (W/L)p = 10, λp = 35 mV¯¹, and λñ = 27 mV¯¹. Determine the small signal differential-mode voltage gain, Ad ro2₂ (k)| Format: 666.3325280404 704 (kn) Format: 583.38844987004 Ad Format: 73.235927554867 M₁ V10- ip3 M3 fiDi M₁ V+ V™ lo iD2 M₂ iD4 -OVO V₂arrow_forward
- Class B Amplifier q1)If the input is 7.5Vp-p...DATA COLLECTION: What is the IL(peak)? a)7mA 6)mA 5)mA 4)mA q2) DATA COLLECTION: What is the Idc? a)3.84 b)4.82 c)3.82mA d)1.82mA q3)DATA COLLECTION: What is the input power in DC? Power input = 48.45mW Power input = 45.48mW Power input = 44.58mW Power input = 45.84mW q4) DATA COLLECTION: What is the output power in AC? a)18mW b)81mW c)11.8mW d)18.9mW q5)DATA COLLECTION: What is the power dissapated by each transistor? a)35.1mW b)53.1mW c)15.3mW d)13.5mW q6)DATA COLLECTION: What is the efficiency of class B amplifier? a)45% b)40% c)63% d)33% q7)arrow_forward11.13 The i-v characteristic of an n-channel enhancement MOSFET is shown in Figure P11.13(a); a standard amplifier circuit based on the n-channel MOSFET is shown in Figure P11.13(b). Determine the quiescent current ino and drain-to-source voltage vs 2.0 I= 25°C 1.8 1.6 Vas10 V- -9V- 1.4 1.2 8V- 1.0 0.8 7V- 0.6 0.4 5 V= 0.2 3 V- 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 Drain-source voltage vps. V (a) Rp VGD VDD VGS Va Drain current ip, Aarrow_forwardFigure 1(a) shows a series fed class A amplifier circuit. In order to achieve the maximum efficiency, the Q point must be located at the center of the DC load line as shown in Figure 1(b). This generates the maximum output current swing of Icmax (p – p) RC and the maximum output voltage swing is VCEmax(p – p) = Vcc Assume that the maximum input de power is (1 Vcc Pimax(dc) = Vcc!cQ(max)=Vcc \2° Rc. 2Rc Find the maximum efficiency, 7 of this circuit.arrow_forward
- ........ (Figure-1) R. RB= 380kN,Rc= 1kN B = 100, VBB = Vcc=12V RB ww Vec CC ......... I, V CE СЕ V ВЕ BB Q-1-b) Describe briefly the input / output characteristics and application of Common Emitter BJT Configurationarrow_forward26 Determine Vị and I, for the two-stage amplifier shown in the circult of Figure P11.26, with identical MOSFETS having K =1 A/V? and Vr =3V, for a. VG = 4 V, b. VG = 5 V c. VG = 4+0.1 cos(750) %3Darrow_forward4. A Darlington transistor is essentially an array of two transistors connected as shown below. Assume both transistors follow our simple model with a current gain of B=100. Determine the maximum value of R2 that will just saturate the transistors, and pass full current through the load resistance R1. v2 V2 R2 PULSE (0 5 0) Q2 NPN R1 10 Q1 NPN V1 24arrow_forward
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