(a) A differential-amplifier has a differential-mode gain of A d = 250 and a common-mode rejection ratio of CMRR dB = ∞ . A differential-mode input signal of v d = 1.5 sin ω t mV is applied along with a common-mode input signal of v c m = 3 sin ω t V. Assuming the common-mode gain is positive, determine the output voltage. (b) Repeat part (a) if the common-mode Rejection ratio is CMRR dB = 80 dB . (c) Repeat part (a) if the common mode rejection ratio is CMRR dB = 50 dB .
(a) A differential-amplifier has a differential-mode gain of A d = 250 and a common-mode rejection ratio of CMRR dB = ∞ . A differential-mode input signal of v d = 1.5 sin ω t mV is applied along with a common-mode input signal of v c m = 3 sin ω t V. Assuming the common-mode gain is positive, determine the output voltage. (b) Repeat part (a) if the common-mode Rejection ratio is CMRR dB = 80 dB . (c) Repeat part (a) if the common mode rejection ratio is CMRR dB = 50 dB .
Solution Summary: The author calculates the CMRR value by comparing the values of the input voltage and the output voltage.
(a) A differential-amplifier has a differential-mode gain of
A
d
=
250
and a common-mode rejection ratio of CMRR
dB
=
∞
.
A differential-mode input signal of
v
d
=
1.5
sin
ω
t
mV
is applied along with a common-mode input signal of
v
c
m
=
3
sin
ω
t
V. Assuming the common-mode gain is positive, determine the output voltage. (b) Repeat part (a) if the common-mode Rejection ratio is CMRR
dB
=
80
dB
. (c) Repeat part (a) if the common mode rejection ratio is
CMRR
dB
=
50
dB
.
C. A variable capacitor.
O d. An amplifier.
When operating in the saturation region, the current gain 'B' of the bipolar transistor increases
Select one:
OTrue
O False
Assume Is= 8x 105 A, B-100, and VA =-. For the circuit shown below and for -0.5 mA, the value of the transconduce
Vcc=2 V
Q1
Adiff-amp is biased with a constant-current source lo- 0.25mA that has an output resistance of R. - 8MO. The bipolar transistor parameters are B=100, VT = 0.025 V and VA -.
Determine the common-mode input resistance.
O a. Ricm = 538 MA
O b.Ricm- 308 MO
OC Ricm = 808 MO
Od Ricm = 704 MQ
Design a three-stage amplifier that is impedance matched (use an emitter follower in stage 2) with an overall voltage gain of approximately 400. The phase of the input and output signal should be maintained. The amplifier should have a usable bandwidth of approximately 20MHz. As engineers you are expected to provide mathematical calculations, circuit diagrams and simulations in multisim software. The simulations should show a sample input signal, its output signal and frequency response plot of the three-stage amplifier.
Need a deep-dive on the concept behind this application? Look no further. Learn more about this topic, electrical-engineering and related others by exploring similar questions and additional content below.