Consider the current source in Figure 10.2(b). The circuit is biased at V + = 2.5 V and V − = − 2.5 V . The transistor parameters are β ≅ ∞ , V A = ∞ , and I S 2 = 10 − 15 A . The circuit is to be designed such that I O = 0.25 m A and the power dissipated in the circuit is no greater than1.8 mW. (a) Determine the maximum value of I R E F , (b) the required valueof I S 1 and (c) the required value of R 1 .
Consider the current source in Figure 10.2(b). The circuit is biased at V + = 2.5 V and V − = − 2.5 V . The transistor parameters are β ≅ ∞ , V A = ∞ , and I S 2 = 10 − 15 A . The circuit is to be designed such that I O = 0.25 m A and the power dissipated in the circuit is no greater than1.8 mW. (a) Determine the maximum value of I R E F , (b) the required valueof I S 1 and (c) the required value of R 1 .
Solution Summary: The author calculates the power dissipation expression for the circuit: I_REF=0.11mA.
Consider the current source in Figure 10.2(b). The circuit is biased at
V
+
=
2.5
V
and
V
−
=
−
2.5
V
. The transistor parameters are
β
≅
∞
,
V
A
=
∞
, and
I
S
2
=
10
−
15
A
. The circuit is to be designed such that
I
O
=
0.25
m
A
and the power dissipated in the circuit is no greater than1.8 mW. (a) Determine the maximum value of
I
R
E
F
, (b) the required valueof
I
S
1
and (c) the required value of
R
1
.
3. In the figure shown below, Vmax is measured as 5.9 V and V min measured as
1.2V.
18] In the figure shown below, is measured as 5.9 V an
(a) Determine the value of V..
(b) Determine the value of Vm.
(c) Determine the modulation index.
(d) Suppose we can change the value of V. What is the maximum value that we
could use for Vm without causing overmodulation?
Draw, Illustrate and label your schematic diagram before solving the problem.
3) Given an Emitter-Stabilize Biased transistor circuit with beta DC is 250,Base resistor is 150 ohms, collector resistor is 1.5k ohms ,emitter resistor is 500 ohms ,emitter voltage supply is -5v and Voltage at common collector is +28V,Voltage at Base-emitter junction is 0.7v,. Determine Base current, Collector current and Voltage at collector-emitter junction.
4. For the transistor in the figure shown below, the parameters are ß = 100 and VÀ = ∞.
a. Design the circuit such that lEQ = 1mA and the Q-pt is in the center of the dc load line.
b. If the peak-to-peak sinusoidal output voltage is 4V, determine the peak-to-peak sinusoidal
signals at the base of the transistor and the peak-to-peak value of Vs.
If the load resistor R₁ = 1kQ is connected to the output through a coupling capacitor,
determine the peak-to-peak value in the output voltage, assuming vs is equal to the value
determined in part (b).
Vcc=+10 V
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Rs = 0.7 kΩ
Cc
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RB
RE
vo
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