Microelectronics: Circuit Analysis and Design
4th Edition
ISBN: 9780073380643
Author: Donald A. Neamen
Publisher: McGraw-Hill Companies, The
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Chapter 16, Problem 16.83P
To determine
To show: The given circuit is a J-K flip flop.
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Students have asked these similar questions
Build frequency dividers, divide-by-2 and divide-by-4 circuit using
a. D Flip Flops
b. JK Flip Flops
You should build 4 circuits in total.
D Flip-Flop
JK Flip-Flop
D Q
J Q
CLK
CLK
K
Preliminary Work
Draw truth tables and logic diagrams of the designs.
Construct and test the designed circuits in Quartus II.
Equipments
D Flip Flop (74LS74). IK Flin Flop (74LS76)
Design Asynchronous counter using negative edge J-K flip flop to count the following
states ( 10→ 9→ 5→4→3→2→1→0). Draw the output wave form of the
counter .
Q#01: The schematic shown in figure below is for Divide_by_11, a frequency divider, that divides
clk by 11 and asserts its output for one cycle. The unit consists of a chain toggle-type flip-flops
with additional logic to form an output pulse every 11th pulse of clk. The asynchronous signal rst is
active-low and drives Q to 1. Develop and verify a model of Divide_by_11.
Vcc
20LSB
Q2
03MSB
clk
clk
clk
clk
clk
rst
rst
rst
rst
wl
w2
clk QB
cik_by_11
rst
rst
Chapter 16 Solutions
Microelectronics: Circuit Analysis and Design
Ch. 16 - Consider the NMOS inverter with resistor load in...Ch. 16 - The enhancementload NMOS inverter in Figure...Ch. 16 - Prob. 16.3EPCh. 16 - Prob. 16.4EPCh. 16 - Consider the NMOS inverter with enhancement load,...Ch. 16 - Prob. 16.2TYUCh. 16 - (a) Consider the results of Exercise Ex 16.1....Ch. 16 - Prob. 16.5EPCh. 16 - Prob. 16.6EPCh. 16 - (a) Design a threeinput NMOS NOR Logic gate with...
Ch. 16 - Consider the NMOS logic circuit in Figure 16.18....Ch. 16 - Repeat Exercise TYU 16.5 for the NMOS logic...Ch. 16 - The CMOS inverter in Figure 16.21 is biased at...Ch. 16 - swA CMOS inverter is biased at VDD=3V . The...Ch. 16 - A CMOS inverter is biased at VDD=1.8V . The...Ch. 16 - Prob. 16.7TYUCh. 16 - Repeat Exercise Ex 16.9 for a CMOS inverter biased...Ch. 16 - Determine the transistor sizes of a 3input CMOS...Ch. 16 - Design the widthtolength ratios of the transistors...Ch. 16 - Design a static CMOS logic circuit that implements...Ch. 16 - Prob. 16.10TYUCh. 16 - Prob. 16.11TYUCh. 16 - Sketch a clocked CMOS logic circuit that realizes...Ch. 16 - Prob. 16.12EPCh. 16 - Prob. 16.13TYUCh. 16 - Consider the CMOS transmission gate in Figure...Ch. 16 - Prob. 16.15TYUCh. 16 - Prob. 16.14EPCh. 16 - Prob. 16.16TYUCh. 16 - Prob. 16.17TYUCh. 16 - Sketch the quasistatic voltage transfer...Ch. 16 - Sketch an NMOS threeinput NOR logic gate. Describe...Ch. 16 - Discuss how more sophisticated (compared to the...Ch. 16 - Sketch the quasistatic voltage transfer...Ch. 16 - Discuss the parameters that affect the switching...Ch. 16 - Prob. 6RQCh. 16 - Sketch a CMOS threeinput NAND logic gate. Describe...Ch. 16 - sDiscuss how more sophisticated (compared to the...Ch. 16 - Prob. 9RQCh. 16 - Sketch an NMOS transmission gate and describe its...Ch. 16 - Sketch a CMOS transmission gate and describe its...Ch. 16 - Discuss what is meant by pass transistor logic.Ch. 16 - Prob. 13RQCh. 16 - Prob. 14RQCh. 16 - Prob. 15RQCh. 16 - Describe the basic architecture of a semiconductor...Ch. 16 - ‘Sketch a CMOS SRAM cell and describe its...Ch. 16 - Prob. 18RQCh. 16 - Describe a maskprogrammed MOSFET ROM memory.Ch. 16 - Describe the basic operation of a floating gate...Ch. 16 - Prob. 16.1PCh. 16 - Prob. 16.2PCh. 16 - (a) Redesign the resistive load inverter in Figure...Ch. 16 - Prob. D16.4PCh. 16 - Prob. 16.5PCh. 16 - Prob. D16.6PCh. 16 - Prob. 16.7PCh. 16 - Prob. 16.8PCh. 16 - For the depletion load inverter shown in Figure...Ch. 16 - Prob. 16.10PCh. 16 - Prob. D16.11PCh. 16 - Prob. D16.12PCh. 16 - Prob. 16.13PCh. 16 - For the two inverters in Figure P16.14, assume...Ch. 16 - Prob. 16.15PCh. 16 - Prob. 16.16PCh. 16 - Prob. 16.17PCh. 16 - Prob. 16.18PCh. 16 - Prob. D16.19PCh. 16 - Prob. 16.20PCh. 16 - Prob. 16.21PCh. 16 - Prob. 16.22PCh. 16 - In the NMOS circuit in Figure P16.23, the...Ch. 16 - Prob. 16.24PCh. 16 - Prob. 16.25PCh. 16 - Prob. 16.26PCh. 16 - What is the logic function implemented by the...Ch. 16 - Prob. D16.28PCh. 16 - Prob. D16.29PCh. 16 - Prob. 16.31PCh. 16 - Prob. 16.32PCh. 16 - Prob. 16.33PCh. 16 - Consider the CMOS inverter pair in Figure P16.34....Ch. 16 - Prob. 16.35PCh. 16 - Prob. 16.36PCh. 16 - Prob. 16.37PCh. 16 - Prob. 16.38PCh. 16 - Prob. 16.39PCh. 16 - (a) A CMOS digital logic circuit contains the...Ch. 16 - Prob. 16.41PCh. 16 - Prob. 16.42PCh. 16 - Prob. 16.43PCh. 16 - Prob. 16.44PCh. 16 - Prob. 16.45PCh. 16 - Prob. 16.46PCh. 16 - Prob. 16.47PCh. 16 - Prob. 16.48PCh. 16 - Prob. 16.49PCh. 16 - Prob. 16.50PCh. 16 - Prob. 16.51PCh. 16 - Prob. 16.52PCh. 16 - Prob. D16.53PCh. 16 - Figure P16.54 is a classic CMOS logic gate. (a)...Ch. 16 - Figure P16.55 is a classic CMOS logic gate. (a)...Ch. 16 - Consider the classic CMOS logic circuit in Figure...Ch. 16 - (a) Given inputs A,B,C,A,B and C , design a CMOS...Ch. 16 - (a) Given inputs A, B, C, D, and E, design a CMOS...Ch. 16 - (a) Determine the logic function performed by the...Ch. 16 - Prob. D16.60PCh. 16 - Prob. 16.61PCh. 16 - Prob. 16.62PCh. 16 - Sketch a clocked CMOS domino logic circuit that...Ch. 16 - Sketch a clocked CMOS domino logic circuit that...Ch. 16 - Prob. D16.65PCh. 16 - Prob. 16.66PCh. 16 - Prob. 16.67PCh. 16 - The NMOS transistors in the circuit shown in...Ch. 16 - Prob. 16.69PCh. 16 - Prob. 16.70PCh. 16 - Prob. 16.71PCh. 16 - (a) Design an NMOS pass transistor logic circuit...Ch. 16 - Prob. 16.73PCh. 16 - What is the logic function implemented by the...Ch. 16 - Prob. 16.75PCh. 16 - Prob. 16.76PCh. 16 - Prob. 16.77PCh. 16 - Consider the NMOS RS flipflop in Figure 16.63...Ch. 16 - Prob. 16.79PCh. 16 - Consider the circuit in Figure P16.80. Determine...Ch. 16 - Prob. D16.81PCh. 16 - Prob. 16.82PCh. 16 - Prob. 16.83PCh. 16 - Prob. 16.84PCh. 16 - (a) A 1 megabit memory is organized in a square...Ch. 16 - Prob. 16.86PCh. 16 - Prob. 16.87PCh. 16 - Prob. 16.88PCh. 16 - Prob. D16.89PCh. 16 - Prob. 16.90PCh. 16 - Prob. 16.91PCh. 16 - Prob. 16.92PCh. 16 - Prob. D16.93PCh. 16 - Prob. D16.94PCh. 16 - Prob. D16.95PCh. 16 - An analog signal in the range 0 to 5 V is to be...Ch. 16 - Prob. 16.97PCh. 16 - Prob. 16.98PCh. 16 - Prob. 16.99PCh. 16 - The weightedresistor D/A converter in Figure 16.90...Ch. 16 - The Nbit D/A converter with an R2R ladder network...Ch. 16 - Prob. 16.102PCh. 16 - Prob. 16.103PCh. 16 - Prob. 16.104PCh. 16 - Prob. 16.105PCh. 16 - Design a classic CMOS logic circuit that will...Ch. 16 - Prob. D16.111DPCh. 16 - Prob. D16.112DPCh. 16 - Prob. D16.113DP
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- For the frequency divider circuit the D-flip-flop is a CD4013 Dual D-Type flip-flop V2 is a square wave applied to the Clock input and Q is the ouput waveform. a. What is the frequency of the square wave Clock from V29? b. What is the frequency of the output pin Q? c. How many D-flip-flops are implemented in the CD4013 Chip? d. How many outputs are implemented in each D-flip-flop? List them.arrow_forwardCompare the circuits, characteristic tables, and the timing diagrams of SR Flip-flops, JK flip-flops, and D flip flops. In your own words, describe the similarity and differences in behavior of these flip flops. Then go on to make comparison between Mealy and Moore machines, first describe each FSM and then elaborate on the similarity and differences between them.arrow_forwarda) Kindly design a Master-slave J-K flip-flop using NAND gates only and state race-around condition, and how it can be eliminated in a Master-slave J-K flipflop? A multiplexer (MUX) also known as data selector, is a logic circuit which allows the digital information from multi-inputs to a single output line(b) Design a 8 to 1 multiplexer by using the four variable function given by F (A, B, C, D) = ∑m = (013489 15) (c) OUR school AIT has lockers in all the campus that she often rent them out to students who needs them, upon graduation they are taken back by the school authorities. Kindly express the process of opening this locker in terms of digital operation.arrow_forward
- D. Design a sequential circuit with eight (8) states and the state transitions are defined in the table shown below. (a) Derive the state table with JK flip-flop inputs using the JK flip-flop excitation table. (b) Derive the JK flip-flop input equations. Present State a b C d h Next State x = 0 8 d f 8 x = 1 b C e a C b h a Output x = 0 0 0 0 1 0 1 x = 1 0 0 0 0 0 1 0arrow_forwardDesign circuit that has an input w and an output z. The circuit is a sequence detector that produces z = 1 when the previous two values of w were 00 or 11; otherwise z = 0. Use W=0101100010101110101011100010 a) For this problem design the circuit using JK flipflops, draw the state diagram, true table, logic circuit.arrow_forwardDetermine the output Q for the given J-K flip flop and the waveforms. HIGH PRE J. CLR PRE %3D 3Darrow_forward
- 4- Draw the output waveform if the signal shown in Figure below is applied to inputs of J-K Flip-Flop. Q is initially LOW. PR HIGH CLK- K CLR CLK- PR CLRarrow_forwardQ.6 Given a sequential circuit implemented using two JK flip-flop as in Figure Q.6a. Analyse the circuit by completing the timing waveform given in Figure Q.6b. QA QB Vcc SET SET J K CLR Q K CLR CLEAR Clk Figure Q.6a Clk CLEAR QA Qs Figure Q.6barrow_forward1. Floating Point Numbersa. Show the difference between IEEE 16, 32, 64, 128-bit floating-point numbers.b. Express the following numbers in hexadecimal IEEE 32-bit floating-pointformat. i. 320ii. -622. Design a circuit that implements function p below using AND, OR, and NOT gates.DO NOT change the form of the equation. ?(?0, ?1, ?2, ) = {?2(?0?1 + ?̅0?̅1)}. (?̅2 + ?̅1)4. Show how the unsigned serial multiplication method would compute M × Q where M = 10110and Q = 01101. M and Q are unsigned numbers. For each step, describe in words what is happening (shift left, shift right, add/subtract M or Q into product, set a bit, etc.), and showthe product (or partial product) for that step. (Note: Q is the multiplier and M is themultiplicand.)arrow_forward
- please help me out. Details and explanations are very much appreciated. Asynchronous JK Flip-flop– Refer to the Waveform number 2. Assuming the initial state is Q = 0, draw the waveform of Q.arrow_forwardElectrical Engineering A Explain Digital IC specification using a neat diagram. B Design a circuit using AOI logic which outputs a 1 when a 4-bit BCD code translated to a number that uses the lower right segment of a 7-segement display. 0828956389 C Design a synchronous counter using D flip flops that counts 2, 3, 5, 7, 10, 12, 14 The unused states of the counter change to 6 at the next clock pulse. An asynchronous sequential eirenit ie dasasiarrow_forwardAn equation in reduced SOP form, is F=AB+B'C+A'C'. I need to draw a logic circuit F using NOT/AND/OR and logoc circuit F using all NAND gates. Thank you for the help. I understood the previous types of gates but I am confused on how to draw these circuits.arrow_forward
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Introduction to Logic Gates; Author: Computer Science;https://www.youtube.com/watch?v=fw-N9P38mi4;License: Standard youtube license