Chapter 16, Problem 16.1TYU

Consider the NMOS inverter with enhancement load, as shown in Figure 16.5(a), biased at $V_{DD}=1.8\text{V}$ . The threshold voltages are $V_{TND}=V_{TNL}=0.4\text{V}$ . Assume ${k^{\prime }}_n=100\mu {\text{A/V}}^{\text{2}}$ . Design the width−to−length ratios such that the output voltage is 0.12 V and the maximum inverter power dissipation is 0.50 mW when ${\upsilon }_I=1.4\text{V}$ . Neglect the body effect. (Ans. ${\left(W/L\right)}_L=3.39$ , ${\left(W/L\right)}_D=24.6$ )