Chapter 16, Problem 16.78P

Consider the NMOS R−S flip−flop in Figure 16.63 biased at $V_{DD}=2.5\text{V}$ . The threshold voltages are 0.4 V (enhancement−mode devices) and −0.6 V (depletion−mode devices). The conduction parameters are $K_3/K_6=40\mu {\text{A/V}}^{\text{2}}$ , $K_2/K_5=100\mu {\text{A/V}}^{\text{2}}$ , and $K_1/K_4=150\mu {\text{A/V}}^{\text{2}}$ . If $Q=\text{logic }0$ and $\bar{Q}=\text{logic 1}$ initially, determine the voltage at S that will cause the flip−flop to change states.