Chapter 16, Problem 16.14TYU

Consider the CMOS transmission gate in Figure 16.56(a). Assume transistor parameters of $V_{TN}=0.4\text{V}$ and $V_{TP}=-0.4\text{V}$ . When $\varphi =2.5\text{V}$ , the input voltage ${\upsilon }_I$ varies with time as ${\upsilon }_I=2.5-0.2t$ for $0\le t\le 12.5\text{s}$ . Let ${\upsilon }_O\left(t=0\right)=2.5\text{V}$ and assume $C_L=0.2\text{pF}$ . Determine the range of times that the NMOS and PMOS devices are conducting. (Ans. NMOS conducting for $2\le t\le 12.5\text{s}$ ; PMOS conducting for $0\le t\le 10.5\text{s}$ ).