Computer Systems: A Programmer's Perspective (3rd Edition)
Computer Systems: A Programmer's Perspective (3rd Edition)
3rd Edition
ISBN: 9780134092669
Author: Bryant, Randal E. Bryant, David R. O'Hallaron, David R., Randal E.; O'Hallaron, Bryant/O'hallaron
Publisher: PEARSON
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Chapter 6.4, Problem 6.15PP

A)

Explanation of Solution

Cache entry and cache byte:

The program running on a machine references the 1-byte word at address “Ox1FE4”. Hexadecimal is a number system of base 16As and as  hex system has 16 digits, the extra needed 6 digits are represented by the first 6 letters of English alphabet which means “ 0,1,2,3,4,5,6,7,8” represents “9,A,?B,?C,?D,?E,?F” respectively in decimal system.

First, one needs to convert the hexadecimal address into binary form:

(0x1FE4)16 = (001874)10=(0000 0000 0001 1111 1110 0100)2

One needs to consider the following set associative (S, E, B, m) = (8, 4, 4, 13). The derived value will be as follows:

The Index (CI):

s=log2(S)   =log2(23) = 3 log2(2) =x

B)

Explanation of Solution

Memory reference:

The address format (1 bit per box) for address “Ox1FE4” is hence represented as:

CTCTCTCTCTCTCTCTCICICICOCO
1111111100100

The memory reference for the above address format “O

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Electrical Engineering 1.) Consider the following series of address references, given as byte addresses: 4. 16, 32, 20, 80, 68, 76, 224, 36, 44, 16, 172, 20, 24, 36, 68 Label each reference as a hit or miss, and show the final cache contents, for each of the following caches. Assume LRU replacement (where appropriate). a.) Direct-mapped, 16x 4-byte blocks. b.) Direct-mapped, 16-byte blocks, total size of 64 bytes. c.) Two-way set associative, 4-byte blocks, total size of 64 bytes. d.) Fully associative, 4-byte blocks, total size of 64 bytes.
Please help with detailed explanation for problem C, don't copy solutions from other sources. Consider a byte addressing architecture with 64-bit memory addresses. a)Which bits of the address would be used in the tag, index and offset in a direct-mapped cache with 512 1-word blocks. b)Which bits of the address would be used in the tag, index and offset in a direct-mapped cache with 64 8-word blocks. c)What is the ratio of bits used for storing data to total bits stored in the cache in each of the above cases a and b?
Q3) A computer system has 1 Mbyte of main memory, 16 bytes block size, and 64 Kbytes cache memory. a. For the main memory addresses of CABBE, 01234, and, FO010 find tag, cache line address, and word offsets for a direct- mapped cache, b. Give any two main memory addresses with different tags that map to the same cache slot for a direct-mapped cache. c. For the main memory addresses of CABBE and, FO010 find tag and word offset values for a fully-associative cache, d. For the main memory addresses of CABBE and, FOO10 find tag, cache set, and word offset values for a two-way set- associative cache.
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