Computer Systems: A Programmer's Perspective (3rd Edition)
3rd Edition
ISBN: 9780134092669
Author: Bryant, Randal E. Bryant, David R. O'Hallaron, David R., Randal E.; O'Hallaron, Bryant/O'hallaron
Publisher: PEARSON
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Question
Chapter 6.1, Problem 6.5PP
A.
Program Plan Intro
Lifetime of SSD:
Intel guarantees about 128 petabytes or PB (
1 PB =
B.
Program Plan Intro
Lifetime of SSD:
Intel guarantees about 128 petabytes or PB (
1 PB =
C.
Program Plan Intro
Lifetime of SSD:
Intel guarantees about 128 petabytes or PB (
1 PB =
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Q2: Consider a non-overlapped memory system that has two levels of memories.
The cache memory has an access time of 100 ns and the RAM memory has an
access time of 1200 ns.
If the effective access time is 50% greater than the cache access time. What
is the hit ratio H?
As we have seen, a potential drawback of SSDs is that the underlying flash memory can wear out. For example, for the SSD in (Figure 1), Intel guarantees about 128 petabytes (128×1015128×1015 bytes) of writes before the drive wears out. Given this assumption, estimate the lifetime (in years) of this SSD for the following workloads:
Worst case for sequential writes: The SSD is written to continuously at a rate of 470 MB/sMB/s (the average sequential write throughput of the device).
Express your answer as an integer.
Worst case for random writes: The SSD is written to continuously at a rate of 303 MB/sMB/s (the average random write throughput of the device).
Express your answer as an integer.
Average case: The SSD is written to at a rate of 20 GB/dayGB/day (the average daily write rate assumed by some computer manufacturers in their mobile computer workload simulations).
Express your answer as an integer.
at least 190 ns?
Q2.
Develop a 64-bit wide memory interface that contains SRAM at locations (EEFE80000-
EEFEFFFFF) H and EPROM at locations (FF2F00000-FF2FFFFFF) H for the Pentium II µp
using 16L8 as a PLA decoder circuit. For the hypotheses 80xxx µp, if we decide to
modify the bit wide memory to 32-bit, suggest the memory locations for both memory
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If you know that, the required time for reading from any single EPROM chip is 950 ns
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Chapter 6 Solutions
Computer Systems: A Programmer's Perspective (3rd Edition)
Ch. 6.1 - Prob. 6.1PPCh. 6.1 - Prob. 6.2PPCh. 6.1 - Prob. 6.3PPCh. 6.1 - Prob. 6.4PPCh. 6.1 - Prob. 6.5PPCh. 6.1 - Prob. 6.6PPCh. 6.2 - Prob. 6.7PPCh. 6.2 - Prob. 6.8PPCh. 6.4 - Prob. 6.9PPCh. 6.4 - Prob. 6.10PP
Ch. 6.4 - Prob. 6.11PPCh. 6.4 - Prob. 6.12PPCh. 6.4 - Prob. 6.13PPCh. 6.4 - Prob. 6.14PPCh. 6.4 - Prob. 6.15PPCh. 6.4 - Prob. 6.16PPCh. 6.5 - Prob. 6.17PPCh. 6.5 - Prob. 6.18PPCh. 6.5 - Prob. 6.19PPCh. 6.5 - Prob. 6.20PPCh. 6.6 - Prob. 6.21PPCh. 6 - Prob. 6.22HWCh. 6 - Prob. 6.23HWCh. 6 - Suppose that a 2 MB file consisting of 512-byte...Ch. 6 - The following table gives the parameters for a...Ch. 6 - The following table gives the parameters for a...Ch. 6 - Prob. 6.27HWCh. 6 - This problem concerns the cache in Practice...Ch. 6 - Suppose we have a system with the following...Ch. 6 - Suppose we have a system with following...Ch. 6 - Suppose that a program using the cache in Problem...Ch. 6 - Repeat Problem 6.31 for memory address0x16E8 A....Ch. 6 - Prob. 6.33HWCh. 6 - Prob. 6.34HWCh. 6 - Prob. 6.35HWCh. 6 - Prob. 6.36HWCh. 6 - Prob. 6.37HWCh. 6 - Prob. 6.38HWCh. 6 - Prob. 6.39HWCh. 6 - Given the assumptions in Problem 6.38, determine...Ch. 6 - You are writing a new 3D game that you hope will...Ch. 6 - Prob. 6.42HWCh. 6 - Prob. 6.43HWCh. 6 - Prob. 6.45HWCh. 6 - Prob. 6.46HW
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