Computer Systems: A Programmer's Perspective (3rd Edition)
3rd Edition
ISBN: 9780134092669
Author: Bryant, Randal E. Bryant, David R. O'Hallaron, David R., Randal E.; O'Hallaron, Bryant/O'hallaron
Publisher: PEARSON
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Expert Solution & Answer
Chapter 6.4, Problem 6.16PP
Explanation of Solution
Deriving addresses that will hit the set:
The address format (1 bit per box) for address is given as:
12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CT | CT | CT | CT | CT | CT | CT | CT | CI | CI | CI | CO | CO |
One can derive the addresses that will hit the set in the following ways:
One needs to consider the following set associative (S, E, B, m) = (8, 4, 4, 13). The derived value will be as follows:
The Index (CI):
The block off set (CO):
Expert Solution & Answer
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(c) The following Sigma 16 program has been loaded into memory at address 0000:
load R3,y[RO]
load R4,x[RO]
lea R5, 2[RO]
sub R1,R4,R3
mul R2,R1,R5
store R2,w[RO]
trap RO,RO,RO
x data 10
y data 12
w data 0
Show the content of the memory writing hexadecimal representation and using a
table with 3 columns: the memory address, the contents of that memory address,
and an explanation of what "the content (of that memory address) means". As a
reference, here are the opcodes for RRR instructions: add 0, sub 1, mul 2, trap c.
And here the opcodes for RX instructions: lea 0, load 1, store 2.
[7]
DO B part if do able
A Instruction Set Architecture
A.1 Instruction set
We present a list of instructions typical of a RISC (reduced instruction set computer) machine. In data-movement and control instructions, the addresses may be immediate #X, direct (memory) M, indirect (memory) [M], register r, or register indirect [r] addresses. Data-processing instructions use immediate or register addressing. PC is the programme counter and a <- b indicates that the value of b is placed in a.
LOAD a, b a <- b
STOR a, b a <- b
ADD a, b, c a <- b + c
ASH a, b, c a <- (b >>[s] c)
LSH a, b, c a <- (b >>[u] c) BR a PC <- a
SUB
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b,
c
a
<-
b
- c
BEQ
a,
b,
c
PC
<-
a
if
b =
c
MUL
a,
b,
c
a
<-
b
* c
BNE
a,
b,
c
PC
<-
a
if
not
b = c
DIV
a,
b,
c
a
<-
b…
Problem
Question 03 (CO3) [0.5 + 0.5 = 1]: Given below are the contents of several Intel 8086 registers
and PHYSICAL memory addresses (ALL in hexadecimal):
Registers:
Memory Locations [Physical Address] = Contents
[05000] = 3300
[06000] = 4444
[07000] = 5555
[95000] = 367A
[96000] = 6666
[97000] = 10C5
DI = 3000
%3D
BX = 3000
%3D
ВР 3 С345
For the following instructions, determine the contents of AX after the each of the instruction has
been executed:
(а) MOV
(b) MOV
АХ, ВР
АХ, [ВХ+DI]
AX =
AX
Chapter 6 Solutions
Computer Systems: A Programmer's Perspective (3rd Edition)
Ch. 6.1 - Prob. 6.1PPCh. 6.1 - Prob. 6.2PPCh. 6.1 - Prob. 6.3PPCh. 6.1 - Prob. 6.4PPCh. 6.1 - Prob. 6.5PPCh. 6.1 - Prob. 6.6PPCh. 6.2 - Prob. 6.7PPCh. 6.2 - Prob. 6.8PPCh. 6.4 - Prob. 6.9PPCh. 6.4 - Prob. 6.10PP
Ch. 6.4 - Prob. 6.11PPCh. 6.4 - Prob. 6.12PPCh. 6.4 - Prob. 6.13PPCh. 6.4 - Prob. 6.14PPCh. 6.4 - Prob. 6.15PPCh. 6.4 - Prob. 6.16PPCh. 6.5 - Prob. 6.17PPCh. 6.5 - Prob. 6.18PPCh. 6.5 - Prob. 6.19PPCh. 6.5 - Prob. 6.20PPCh. 6.6 - Prob. 6.21PPCh. 6 - Prob. 6.22HWCh. 6 - Prob. 6.23HWCh. 6 - Suppose that a 2 MB file consisting of 512-byte...Ch. 6 - The following table gives the parameters for a...Ch. 6 - The following table gives the parameters for a...Ch. 6 - Prob. 6.27HWCh. 6 - This problem concerns the cache in Practice...Ch. 6 - Suppose we have a system with the following...Ch. 6 - Suppose we have a system with following...Ch. 6 - Suppose that a program using the cache in Problem...Ch. 6 - Repeat Problem 6.31 for memory address0x16E8 A....Ch. 6 - Prob. 6.33HWCh. 6 - Prob. 6.34HWCh. 6 - Prob. 6.35HWCh. 6 - Prob. 6.36HWCh. 6 - Prob. 6.37HWCh. 6 - Prob. 6.38HWCh. 6 - Prob. 6.39HWCh. 6 - Given the assumptions in Problem 6.38, determine...Ch. 6 - You are writing a new 3D game that you hope will...Ch. 6 - Prob. 6.42HWCh. 6 - Prob. 6.43HWCh. 6 - Prob. 6.45HWCh. 6 - Prob. 6.46HW
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