Computer Systems: A Programmer's Perspective (3rd Edition)
3rd Edition
ISBN: 9780134092669
Author: Bryant, Randal E. Bryant, David R. O'Hallaron, David R., Randal E.; O'Hallaron, Bryant/O'hallaron
Publisher: PEARSON
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Question
Chapter 6.4, Problem 6.11PP
A.
Program Plan Intro
Given Information:
A hypothetical cache that uses the high order “s” bits of an address as the set index is given. For such a cache, the contiguous chunks of memory blocks are mapped to the same cache sets.
B.
Program Plan Intro
Given Information:
The following code is given:
//traverse the array
for(i=0;i<4096;i++)
{
//add array elements
sum+=array[i];
}
The code runs on a system with cache of the form(S,E,B,m)= (512,1,32,32).
Expert Solution & Answer
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Students have asked these similar questions
Question 3 (Cache Memory Mapping): I
(a) For the main memory address 0:0:0, briefly explain how a search is performed in two-way set
associative mapping. Assume that the main memory size is 4 GB, the cache memory is 8 KB and the size
of cache block is 32 bytes.
(b) A 4-way set associative mapped cache consists of 64 blocks, divided into 4 sets. Main memory consists
of 4K blocks, each containing 128 locations. Complete the following format for the main memory address
by showing all your workings and find the tag size. [Hint: Calculate the no. of locations in the main memory,
which gives the memory size in terms of the total number of bits] ,
Set No.
Block No.
Location Within Block
No. of bits
m
ofessor,
S.
aw-Hill
tion... V
!!!
ar textbook
As described in COD Section 5.7 (Virtual memory), virtual memory uses a page table to track the mapping of virtual addresses to
physical addresses. This exercise shows how this table must be updated as addresses are accessed. The following data constitute a
stream of virtual byte addresses as seen on a system. Assume 4 KiB pages, a four-entry fully associative TLB, and true LRU
replacement. If pages must be brought in from disk, increment the next largest page number.
TLB
Page Table
Decimal 4669 2227 13916 34587 48870 12608 49225
hex 0x123d 0x08b3 0x365c 0x871b Oxbee6 0x3140 0xc049
Valid
1
1
1
0
Index
0
1
2
3
4
5
(a) For each access shown above, list
6
7
8
9
a
b
Tag
Oxb
Ox7
0x3
0x4
Valid
1
0
0
1
1
1
0
1
0
0
1
1
▪ whether the access is a hit or miss in the TLB,
▪ whether the access is a hit or miss in the page table,
▪ whether the access is a page fault,
the updated state of the TLB.
Physical Page
Number
12
4
6
9
Time Since Last
Access
4…
(A) In this exercise we look at memory locality properties of matrix computation. The following code is
written in C, where elements within the same row are stored contiguously. Assume each word is a 64-bit
integer.
for (I-0; I<8; I++)
for (J-0; J<8000; J++)
A[I] [J]-B [I] [0] +A[J] [I];
1. How many 64-bit integers can be stored in a 16-byte cache block?
2. Which variable references exhibit temporal locality?
3. Which variable references exhibit spatial locality?
(B) Locality is affected by both the reference order and data layout. The same computation can also be
written below in Matlab, which differs from C in that it stores matrix elements within the same column
contiguously in memory.
1. How many 64-bit integers can be stored in a 16-byte cache block?
2. Which variable references exhibit temporal locality?
3. Which variable references exhibit spatial locality?
4. How many 16-byte cache blocks are needed to store all 64-bit matrix elements being referenced using
Matlab's matrix…
Chapter 6 Solutions
Computer Systems: A Programmer's Perspective (3rd Edition)
Ch. 6.1 - Prob. 6.1PPCh. 6.1 - Prob. 6.2PPCh. 6.1 - Prob. 6.3PPCh. 6.1 - Prob. 6.4PPCh. 6.1 - Prob. 6.5PPCh. 6.1 - Prob. 6.6PPCh. 6.2 - Prob. 6.7PPCh. 6.2 - Prob. 6.8PPCh. 6.4 - Prob. 6.9PPCh. 6.4 - Prob. 6.10PP
Ch. 6.4 - Prob. 6.11PPCh. 6.4 - Prob. 6.12PPCh. 6.4 - Prob. 6.13PPCh. 6.4 - Prob. 6.14PPCh. 6.4 - Prob. 6.15PPCh. 6.4 - Prob. 6.16PPCh. 6.5 - Prob. 6.17PPCh. 6.5 - Prob. 6.18PPCh. 6.5 - Prob. 6.19PPCh. 6.5 - Prob. 6.20PPCh. 6.6 - Prob. 6.21PPCh. 6 - Prob. 6.22HWCh. 6 - Prob. 6.23HWCh. 6 - Suppose that a 2 MB file consisting of 512-byte...Ch. 6 - The following table gives the parameters for a...Ch. 6 - The following table gives the parameters for a...Ch. 6 - Prob. 6.27HWCh. 6 - This problem concerns the cache in Practice...Ch. 6 - Suppose we have a system with the following...Ch. 6 - Suppose we have a system with following...Ch. 6 - Suppose that a program using the cache in Problem...Ch. 6 - Repeat Problem 6.31 for memory address0x16E8 A....Ch. 6 - Prob. 6.33HWCh. 6 - Prob. 6.34HWCh. 6 - Prob. 6.35HWCh. 6 - Prob. 6.36HWCh. 6 - Prob. 6.37HWCh. 6 - Prob. 6.38HWCh. 6 - Prob. 6.39HWCh. 6 - Given the assumptions in Problem 6.38, determine...Ch. 6 - You are writing a new 3D game that you hope will...Ch. 6 - Prob. 6.42HWCh. 6 - Prob. 6.43HWCh. 6 - Prob. 6.45HWCh. 6 - Prob. 6.46HW
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- a) A block-set associative cache memory consists of 128 blocks divided into four block sets. The main memory consists of 32,768 blocks and each block contains 512 eight-bit words (1) How many bits are required for addressing the main memory? (ii) How many bits are needed to represent the TAG SET and WORD fields? b) Write a program to code the equation X=(A+B)L| ((C+D) using one-address instructions. Please solve only the b partarrow_forwardElectrical Engineering 1.) Consider the following series of address references, given as byte addresses: 4. 16, 32, 20, 80, 68, 76, 224, 36, 44, 16, 172, 20, 24, 36, 68 Label each reference as a hit or miss, and show the final cache contents, for each of the following caches. Assume LRU replacement (where appropriate). a.) Direct-mapped, 16x 4-byte blocks. b.) Direct-mapped, 16-byte blocks, total size of 64 bytes. c.) Two-way set associative, 4-byte blocks, total size of 64 bytes. d.) Fully associative, 4-byte blocks, total size of 64 bytes.arrow_forwardProblem 0. The following table gives some of the parameters for a number of different hardware caches. Fill in the table with the values of the missing parameters. Recall that m is the number of physical address bits, C is the cache size in bytes, B is the block size in bytes, E is the associativity, i.e., lines per set, S is the number of sets, t is the number of tag bits, s is the number of set index bits, and b is the number of block offset bits. Cache m 48 32030 (b) 48 32 24 24 C B E 16384 32 16 32768 64 65536 128 512 32 1024 8 8 4 14 1 4 S b S tarrow_forward
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