Computer Systems: A Programmer's Perspective (3rd Edition)
Computer Systems: A Programmer's Perspective (3rd Edition)
3rd Edition
ISBN: 9780134092669
Author: Bryant, Randal E. Bryant, David R. O'Hallaron, David R., Randal E.; O'Hallaron, Bryant/O'hallaron
Publisher: PEARSON
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Chapter 6, Problem 6.39HW

A)

Program Plan Intro

Given Information:

The given code is:

// define structure

square point_color

{

// variable declaration

int c;

int m;

int y;

int k;

};

// declare structure array

struct point_color square[16][16];

int i,j;

// traverse through the array

for(i=0;i<16;i++)

{

//traverse through elements

for(j=0;j<16;j++)

{

//square all elements of the 2-D array

square[j][i].c=0;

square[j][i].m=0;

square[j][i].y=1;

square[j][i].k=0;

}

}

Write hit:

If the information in the cache is reserved or in dirty state then the cache line is updated in its place without updating memory set from its state to dirty.

  • If the state of information is in valid state then it executes a write-through operation.
  • It then updates the memory and block and changes its blocked state to reserved state.

Write miss:

A partial cache line write is handed as a read miss followed by a write hit. All the other caches are left in the invalid state and the reserved state is occupied by the current state.

B)

Program Plan Intro

Given Information:

The given code is:

// define structure

square point_color

{

// variable declaration

int c;

int m;

int y;

int k;

};

// declare structure array

struct point_color square[16][16];

int i,j;

// traverse through the array

for(i=0;i<16;i++)

{

//traverse through elements

for(j=0;j<16;j++)

{

//square all elements of the 2-D array

square[j][i].c=0;

square[j][i].m=0;

square[j][i].y=1;

square[j][i].k=0;

}

}

Write hit:

If the information in the cache is reserved or in dirty state then the cache line is updated in its place without updating memory set from its state to dirty.

  • If the state of information is in valid state then it executes a write-through operation.
  • It then updates the memory and block and changes its blocked state to reserved state.

Write miss:

A partial cache line write is handed as a read miss followed by a write hit. All the other caches are left in the invalid state and the reserved state is occupied by the current state.

C)

Program Plan Intro

Given Information:

The given code is:

//define structure

square point_color

{

// variable declaration

int c;

int m;

int y;

int k;

};

// declare structure array

struct point_color square[16][16];

int i,j;

// traverse through the array

for(i=0;i<16;i++)

{

//traverse through elements

for(j=0;j<16;j++)

{

//square all elements of the 2-D array

square[j][i].c=0;

square[j][i].m=0;

square[j][i].y=1;

square[j][i].k=0;

}

}

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Students have asked these similar questions
The following table gives the parameters for a number of differentcaches. Your task is to fill in the missing fields in the table. Recall that m is the number of physical address bits, C is the cache size (number of data bytes), B is the block size in bytes, E is the associativity, S is the number of cache sets, t is the number of tag bits, s is the number of set index bits, and b is the number of block offset bits.
This function will be able to determine the fields in a log entry it needs to look at in order to do its job properly. The following line of code computes the average number of cache misses for each item in the cache when 64-byte cache blocks are used without any prefetching being performed by the program.
A computer of 32 bits has a cache memory of 64 KB with a cache line size of 64 bytes. The cache access time is 20 ns, and the miss penalty is 120 ns. The cache is 2-way associative. a) What is the number of cache lines? b) What is the number of cache sets? c) What is the number of lines per set? d) Draw a scheme of this cache. e) Calculate the time to read a word in case of miss.
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