Concept explainers
A)
Given Information:
The given code is:
// define structure
square point_color
{
// variable declaration
int c;
int m;
int y;
int k;
};
// declare structure array
struct point_color square[16][16];
int i,j;
// traverse through the array
for(i=0;i<16;i++)
{
//traverse through elements
for(j=0;j<16;j++)
{
//square all elements of the 2-D array
square[j][i].c=0;
square[j][i].m=0;
square[j][i].y=1;
square[j][i].k=0;
}
}
Write hit:
If the information in the cache is reserved or in dirty state then the cache line is updated in its place without updating memory set from its state to dirty.
- If the state of information is in valid state then it executes a write-through operation.
- It then updates the memory and block and changes its blocked state to reserved state.
Write miss:
A partial cache line write is handed as a read miss followed by a write hit. All the other caches are left in the invalid state and the reserved state is occupied by the current state.
B)
Given Information:
The given code is:
// define structure
square point_color
{
// variable declaration
int c;
int m;
int y;
int k;
};
// declare structure array
struct point_color square[16][16];
int i,j;
// traverse through the array
for(i=0;i<16;i++)
{
//traverse through elements
for(j=0;j<16;j++)
{
//square all elements of the 2-D array
square[j][i].c=0;
square[j][i].m=0;
square[j][i].y=1;
square[j][i].k=0;
}
}
Write hit:
If the information in the cache is reserved or in dirty state then the cache line is updated in its place without updating memory set from its state to dirty.
- If the state of information is in valid state then it executes a write-through operation.
- It then updates the memory and block and changes its blocked state to reserved state.
Write miss:
A partial cache line write is handed as a read miss followed by a write hit. All the other caches are left in the invalid state and the reserved state is occupied by the current state.
C)
Given Information:
The given code is:
//define structure
square point_color
{
// variable declaration
int c;
int m;
int y;
int k;
};
// declare structure array
struct point_color square[16][16];
int i,j;
// traverse through the array
for(i=0;i<16;i++)
{
//traverse through elements
for(j=0;j<16;j++)
{
//square all elements of the 2-D array
square[j][i].c=0;
square[j][i].m=0;
square[j][i].y=1;
square[j][i].k=0;
}
}
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Check out a sample textbook solutionChapter 6 Solutions
Computer Systems: A Programmer's Perspective (3rd Edition)
- Let's pretend that something unexpected happens: the CPU makes a partially-completed request to the cache at the same time as a block is being returned from the write buffer to main memory. The following steps need to take place.arrow_forwardThe following table gives the parameters for a number of differentcaches. For each cache, fill in the missing fields in the table. Recallthat m is the number of physical address bits, C is the cache size(number of data bytes), B is the block size in bytes, E is theassociativity, S is the number of cache sets, t is the number of tag bits, S is the number of set index bits, and b is the number of block offset bits.arrow_forwardThe following blocks are referenced by the CPU and to be fetched from the RAM to the cache sequentially: (ij k L L jmj n L mj m L k sįPi o k) Assume that the cache set is empty and all the above blocks can be inserted into the set. Use the LRU algorithm to fill in the following table that describes the status of the cache locations for each called block .arrow_forward
- Below is a list of 32-bit memory address references, given as memory addresses. 12, 720, 172, 8, 764, 352, 760, 56, 724, 176, 744You would like to access a cache with the given memory addresses. The size of cache is 23 = 8-blocks. Your task is to: (1) find out the binary address, (2) fill out the tag and index for each memory address and (3) indicate whether the access is hit or miss in the following table:arrow_forwardThe following blocks are referenced by the CPU and to be fetched from the RAM to the cache sequentially: (i j k L L j m j n L m j m L k S j P i O k) Assume that the cache set is empty and all the above blocks can be inserted into the set. Use the LRU algorithm to fill in the following table that describes the status of the cache locations for each called block. Note : All numbers must be binaryarrow_forwardProblem 0. The following table gives some of the parameters for a number of different hardware caches. Fill in the table with the values of the missing parameters. Recall that m is the number of physical address bits, C is the cache size in bytes, B is the block size in bytes, E is the associativity, i.e., lines per set, S is the number of sets, t is the number of tag bits, s is the number of set index bits, and b is the number of block offset bits. Cache m 48 32030 (b) 48 32 24 24 C B E 16384 32 16 32768 64 65536 128 512 32 1024 8 8 4 14 1 4 S b S tarrow_forward
- Is there a way to find out which parts of a log entry a certain log processing function can read? The following code determines the typical number of cache misses per entry while using 64-byte cache blocks and no prefetching.arrow_forwardThe memory access time is I nanosecond for read operation with a hit in cache. * nanoseconds for a read operation with a miss in cache, 2 nanoseconds for a write operation with a hit in cache and 10 anoseconds for a write operation with a miss in cache. Execution of a sequence of instructions involves 100 instruction fetch operations, 60 memory operand read operations and 40 memory operand write operations. The cache hit-ratio is 0.9. The average memory access time (in nanoseconds) in executing the sequence of instructions isarrow_forwardExercise 2: A byte addressable memory has a size of 1024 MBytes. This memory is attached to a direct mapping cache of 32KBytes that contains 1024 lines. a. What is the memory address length? b. What is the block size? c. What is the number of blocks in main memory? d. What is the length in bit of: tag (T), line number (L) and byte number (W)? e. Determine in Hexadecimal the tag (T), line number (L) and byte number (W) of the following Hexadecimal memory address: 000008AE f. What is the block that contains the address 000000DE? g. Which line of the cache can hold the block containing 000000DE?arrow_forward
- Job list: Job Number Memory Requested J1 700k J2 500k J3 740k Memory List Memory Block Size Block 1 610k (low - order memory) 850k Block 2 Block 3 700k (high - order memory) a.) Use the best-fit algorithm to allocate the memory blocks to the three arriving jobs b.) Use the first-fit algorithm to allocate the memory blocksto the three arriving jobsarrow_forwardA 2-way set associative cache consists of four sets. Main memory contains 2K blocks of eight words each. Show the main memory address format that allows us to map addresses from main memory to cache. Be sure to include the fields as well as their sizes. Compute the hit ratio for a program that loops 6 times from locations 8 to 51 in main memory. You may leave the hit ratio in terms of a fraction. Please show details how you obtain the result.arrow_forwardThis function will be able to look at which fields in a log entry that it needs to. When you use 64-byte cache blocks and don't prefetch, the following code calculates the average number of cache misses for each entry in the cache.arrow_forward
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