Computer Systems: A Programmer's Perspective (3rd Edition)
3rd Edition
ISBN: 9780134092669
Author: Bryant, Randal E. Bryant, David R. O'Hallaron, David R., Randal E.; O'Hallaron, Bryant/O'hallaron
Publisher: PEARSON
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Textbook Question
Chapter 6, Problem 6.28HW
This problem concerns the cache in Practice Problem 6.12.
- A. List all of the hex memory addresses that will hit in set 2.
- B. List all of the hex memory addresses that will hit in set 4.
- C. List all of the hex memory addresses that will hit in Set 5.
- D. List all of the hex memory addresses that will hit in set 7.
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This problem concerns the cache in Attached problem A. List all of the hex memory addresses that will hit in set 2.B. List all of the hex memory addresses that will hit in set 4.C. List all of the hex memory addresses that will hit in set 5.D. List all of the hex memory addresses that will hit in set 7.
Problem 0. The following table gives some of the parameters for a number of different hardware
caches. Fill in the table with the values of the missing parameters. Recall that m is the number of
physical address bits, C is the cache size in bytes, B is the block size in bytes, E is the associativity,
i.e., lines per set, S is the number of sets, t is the number of tag bits, s is the number of set index
bits, and b is the number of block offset bits.
Cache m
48
32030
(b)
48
32
24
24
C
B
E
16384 32 16
32768 64
65536 128
512 32
1024
8
8
4
14
1
4
S
b
S
t
Q2: a cache memory consists of 512 blocks, and if the last word
in the block is 1111111. I the last Tag is 1111.
Then the total number of words in main memory is
Tags, and
The main memory consists of
blocks. The total number of bits in address fields i .
where number of bits for tag field is ....
and the remaining number of bits for word field i ..
Chapter 6 Solutions
Computer Systems: A Programmer's Perspective (3rd Edition)
Ch. 6.1 - Prob. 6.1PPCh. 6.1 - Prob. 6.2PPCh. 6.1 - Prob. 6.3PPCh. 6.1 - Prob. 6.4PPCh. 6.1 - Prob. 6.5PPCh. 6.1 - Prob. 6.6PPCh. 6.2 - Prob. 6.7PPCh. 6.2 - Prob. 6.8PPCh. 6.4 - Prob. 6.9PPCh. 6.4 - Prob. 6.10PP
Ch. 6.4 - Prob. 6.11PPCh. 6.4 - Prob. 6.12PPCh. 6.4 - Prob. 6.13PPCh. 6.4 - Prob. 6.14PPCh. 6.4 - Prob. 6.15PPCh. 6.4 - Prob. 6.16PPCh. 6.5 - Prob. 6.17PPCh. 6.5 - Prob. 6.18PPCh. 6.5 - Prob. 6.19PPCh. 6.5 - Prob. 6.20PPCh. 6.6 - Prob. 6.21PPCh. 6 - Prob. 6.22HWCh. 6 - Prob. 6.23HWCh. 6 - Suppose that a 2 MB file consisting of 512-byte...Ch. 6 - The following table gives the parameters for a...Ch. 6 - The following table gives the parameters for a...Ch. 6 - Prob. 6.27HWCh. 6 - This problem concerns the cache in Practice...Ch. 6 - Suppose we have a system with the following...Ch. 6 - Suppose we have a system with following...Ch. 6 - Suppose that a program using the cache in Problem...Ch. 6 - Repeat Problem 6.31 for memory address0x16E8 A....Ch. 6 - Prob. 6.33HWCh. 6 - Prob. 6.34HWCh. 6 - Prob. 6.35HWCh. 6 - Prob. 6.36HWCh. 6 - Prob. 6.37HWCh. 6 - Prob. 6.38HWCh. 6 - Prob. 6.39HWCh. 6 - Given the assumptions in Problem 6.38, determine...Ch. 6 - You are writing a new 3D game that you hope will...Ch. 6 - Prob. 6.42HWCh. 6 - Prob. 6.43HWCh. 6 - Prob. 6.45HWCh. 6 - Prob. 6.46HW
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- 5. suppose a computer using fully associative cache has 224 bytes of byte-addressable main memory and a cache of 128 blocks, where each cache block contains 64 bytes. a) how many blocks of main memory are there? b) what is the format of a memory address as seen by the cache ; that is, what are the size of the tag and offset field. c) To which cache block will the memory address 0x01D872 map?arrow_forward1. Suppose a computer has 2³2 bytes of byte-addressable main memory and a cache size of 2¹5 bytes, and each cache block contains 64 bytes. a) How many blocks of main memory are there? (_ b) How many blocks of cache memory are there? (_ c) If this cache is direct-mapped, what is the format of a memory address as seen by the cache; that is, the size of the tag field_ the size of block field and the size of the offset field_ d) If this cache is fully associative, what is the format of a memory address as seen by the cache; that is, the size of the tag field_ and the size of the offset field e) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache; that is, the size of the tag field_ the size of set field and the size of the offset fieldarrow_forwardA computer is using a fully associative cache and has 216 bytes of main memory (byte addressable) and a cache of 64 blocks, where each block contains 32 bytes. a. How many blocks of main memory are there? b. What will be the sizes of the tag, index, and byte offset fields? c. To which cache set will the memory address 0xF8C9(hexadecimal) map?arrow_forward
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