Computer Systems: A Programmer's Perspective (3rd Edition)
3rd Edition
ISBN: 9780134092669
Author: Bryant, Randal E. Bryant, David R. O'Hallaron, David R., Randal E.; O'Hallaron, Bryant/O'hallaron
Publisher: PEARSON
expand_more
expand_more
format_list_bulleted
Videos
Textbook Question
Chapter 6, Problem 6.29HW
Suppose we have a system with the following properties:
• The memory is byte addressable.
• Memory accesses are to 1-byte words (not to 4-byte words).
• Addressed are 12 bits wide.
• The cache is two-way set associative (E= 2), with a 4-byte block size (B = 4) and four sets.(S = 4).
The contents of the cache are as follows, with all addresses, tags and values given in hexadecimal notation:
- A. The following diagram shows the format of an address (1 bit per box). Indicate (by labeling the diagram) the fields that would be used to determine the following:
CO. The cache block offset
CI. The cache set index
CT. The cache tag
- B. For each of the following memory accesses, indicates if it will be a cache hit or miss when carried out in sequence as listed. Also give the value of a read if it can be inferred from the information in the cache.
Expert Solution & Answer
Want to see the full answer?
Check out a sample textbook solution
Students have asked these similar questions
Question 18
Suppose we have a byte-addressable computer using 2-way set associative mapping with 16-bit main memory addresses and 32
blocks of cache. Suppose also that each block contains 8 bytes. The size of the block offset field is
bits, the
bits.
size of the set field is
bits, and the size of the tag hield is
Consider a byte-addressable computer with 32-bit addresses, a cache capable of storing a total of 64K bytes of data, and cache
blocks of size 128 bytes. If the computer uses direct mapping, the format of the memory address is as follows:
bits for the tag field,
bits for the cache block number, and
bits for
the block offset.
Suppose a byte-addressable computer using set associative cache has 2^24 bytes of main memory and a cache size of 64K bytes, and each cache block contains 32 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?
Chapter 6 Solutions
Computer Systems: A Programmer's Perspective (3rd Edition)
Ch. 6.1 - Prob. 6.1PPCh. 6.1 - Prob. 6.2PPCh. 6.1 - Prob. 6.3PPCh. 6.1 - Prob. 6.4PPCh. 6.1 - Prob. 6.5PPCh. 6.1 - Prob. 6.6PPCh. 6.2 - Prob. 6.7PPCh. 6.2 - Prob. 6.8PPCh. 6.4 - Prob. 6.9PPCh. 6.4 - Prob. 6.10PP
Ch. 6.4 - Prob. 6.11PPCh. 6.4 - Prob. 6.12PPCh. 6.4 - Prob. 6.13PPCh. 6.4 - Prob. 6.14PPCh. 6.4 - Prob. 6.15PPCh. 6.4 - Prob. 6.16PPCh. 6.5 - Prob. 6.17PPCh. 6.5 - Prob. 6.18PPCh. 6.5 - Prob. 6.19PPCh. 6.5 - Prob. 6.20PPCh. 6.6 - Prob. 6.21PPCh. 6 - Prob. 6.22HWCh. 6 - Prob. 6.23HWCh. 6 - Suppose that a 2 MB file consisting of 512-byte...Ch. 6 - The following table gives the parameters for a...Ch. 6 - The following table gives the parameters for a...Ch. 6 - Prob. 6.27HWCh. 6 - This problem concerns the cache in Practice...Ch. 6 - Suppose we have a system with the following...Ch. 6 - Suppose we have a system with following...Ch. 6 - Suppose that a program using the cache in Problem...Ch. 6 - Repeat Problem 6.31 for memory address0x16E8 A....Ch. 6 - Prob. 6.33HWCh. 6 - Prob. 6.34HWCh. 6 - Prob. 6.35HWCh. 6 - Prob. 6.36HWCh. 6 - Prob. 6.37HWCh. 6 - Prob. 6.38HWCh. 6 - Prob. 6.39HWCh. 6 - Given the assumptions in Problem 6.38, determine...Ch. 6 - You are writing a new 3D game that you hope will...Ch. 6 - Prob. 6.42HWCh. 6 - Prob. 6.43HWCh. 6 - Prob. 6.45HWCh. 6 - Prob. 6.46HW
Additional Engineering Textbook Solutions
Find more solutions based on key concepts
What is the purpose of testing a program with sample data or input?
Starting Out With Visual Basic (8th Edition)
Each byte in memory is assigned a unique _____
Starting Out with C++: Early Objects
BankCharges Class A bank charges 10 per month, plus the following check fees for a commercial checking account:...
Starting Out with Java: Early Objects (6th Edition)
Write a function called b that takes two arguments: an u and a bit number n. Have the function return 1 bit num...
Programming in C
Write a class LapTimer that can be used to time the laps in a race. The class should have the following private...
Java: An Introduction to Problem Solving and Programming (7th Edition)
Suppose v is a vector of ints. Write a for loop that outputs all the elements of v, except for the first elemen...
Problem Solving with C++ (9th Edition)
Knowledge Booster
Learn more about
Need a deep-dive on the concept behind this application? Look no further. Learn more about this topic, computer-science and related others by exploring similar questions and additional content below.Similar questions
- A computer of 32 bits has a cache memory of 64 KB with a cache line size of 64 bytes. The cache access time is 20 ns, and the miss penalty is 120 ns. The cache is 2-way associative. a) What is the number of cache lines? b) What is the number of cache sets? c) What is the number of lines per set? d) Draw a scheme of this cache. e) Calculate the time to read a word in case of miss.arrow_forwardSuppose a computer using direct-mapped cache has 232 (that's 232)232) bytes of byte-addressable main memory, and a cache size of 512 bytes, and each cache block contains 64 bytes. How many blocks of main memory are there? What is the format of a memory address as seen by cache, i.e. what are the sizes of the tag, block, and offset fields? To which cache block will the memory address 0x13A4498A map?arrow_forwardSuppose a computer using direct mapped cache has 232 words of main memory, and a cache of 1024 blocks, where each cache block contains 32 words. How many blocks of main memory are there? What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag, block, and offset fields? To which cache block will the memory reference 0003101A16 map?arrow_forward
- Suppose a computer using direct mapped cache has 232 byte of byte-addressable main memory, and a cache of 1024 blocks, where each cache block contains 32 bytes. a) How many blocks of main memory are there? b) What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag, block, and offset fields? c) To which cache block will the memory address 0x000063FA map?arrow_forwardA digital computer has a memory unit of 64K X 16 and a cache memory of 1K words. The cache uses direct mapping with a block size of four words.i) How many bits are there in the tag, index, block and word fields of the address format?ii) How many bits are there in each word of cache, and how are they divided into functions? Include a valid bit.iii) How many blocks can the cache accommodate?arrow_forwardSuppose a computer using set associative cache has 216 words of main memory and a cache of 128 blocks, and each cache block contains 8 words. If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields?arrow_forward
- By convention, a cache is named according to the amount of data it contains (ie., a 4 KiB cache can hold 4 KiB of data); however, caches also require SRAM to store metadata such as tags and valid bits. For this exercise, you will examine how a cache's configuration affects the total amount of SRAM needed to implement it as well as the performance of the cache. For all parts, assume that the caches are byte addressable, and that addresses and words are 64 bits. 1. Calculate the total number of bits required to implement a 32 KiB cache with two-word blocks. 2. Calculate the total number of bits required to implement a 64 KiB cache with 16-word blocks. How much bigger is this cache than the 32 KiB cache described in Exercise (1) above? (Notice that, by changing the block size, we doubled the amount of data without doubling the total size of the cache.) 3. Explain why this 64 KiB cache, despite its larger data size, might provide slower performance than the first cache. 4. Generate a…arrow_forwardSuppose a computer using fully associative cache has 224 words of main memory and a cache of 512 blocks, where each cache block contains 16 words. How many blocks of main memory are there? What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag and offset fields? To which cache block will the memory reference 17042416 map?arrow_forwardSuppose we have a system with the following properties:The memory is byte addressable.Memory accesses are to 1-byte words (not to 4-byte words).Addresses are 12 bits wide.The cache is two-way set associative (E = 2), with a 4-byte blocksize (B = 4) and four sets (S = 4).arrow_forward
- Suppose a byte-addressable computer using set associative cache has 8M byes of main memory and a cache of 128 blocks, where each cache block contains 64 bytes. a) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 16-way set associative, what is the format of a memory address as seen by the cachearrow_forwardSuppose a byte-addressable computer using set associative cache has 4Mbyes of main memory and a cache of 64 blocks, where each cache block contains 8 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache? Show all work and explain how you got the answers please. Thanksarrow_forwardSuppose a computer using fully associative cache has 4 GB of byte-addressable main memory and a cache of 256 blocks, where each block contains 256 bytes. a) How many blocks of main memory are there? b) What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag and offset fields? c) To which cache block will the memory address 0X1A1B1C1D map?arrow_forward
arrow_back_ios
SEE MORE QUESTIONS
arrow_forward_ios
Recommended textbooks for you
Database System ConceptsComputer ScienceISBN:9780078022159Author:Abraham Silberschatz Professor, Henry F. Korth, S. SudarshanPublisher:McGraw-Hill Education
Starting Out with Python (4th Edition)Computer ScienceISBN:9780134444321Author:Tony GaddisPublisher:PEARSON
Digital Fundamentals (11th Edition)Computer ScienceISBN:9780132737968Author:Thomas L. FloydPublisher:PEARSON
C How to Program (8th Edition)Computer ScienceISBN:9780133976892Author:Paul J. Deitel, Harvey DeitelPublisher:PEARSON
Database Systems: Design, Implementation, & Manag...Computer ScienceISBN:9781337627900Author:Carlos Coronel, Steven MorrisPublisher:Cengage Learning
Programmable Logic ControllersComputer ScienceISBN:9780073373843Author:Frank D. PetruzellaPublisher:McGraw-Hill Education
Database System Concepts
Computer Science
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:McGraw-Hill Education
Starting Out with Python (4th Edition)
Computer Science
ISBN:9780134444321
Author:Tony Gaddis
Publisher:PEARSON
Digital Fundamentals (11th Edition)
Computer Science
ISBN:9780132737968
Author:Thomas L. Floyd
Publisher:PEARSON
C How to Program (8th Edition)
Computer Science
ISBN:9780133976892
Author:Paul J. Deitel, Harvey Deitel
Publisher:PEARSON
Database Systems: Design, Implementation, & Manag...
Computer Science
ISBN:9781337627900
Author:Carlos Coronel, Steven Morris
Publisher:Cengage Learning
Programmable Logic Controllers
Computer Science
ISBN:9780073373843
Author:Frank D. Petruzella
Publisher:McGraw-Hill Education
Instruction Format (With reference to address); Author: ChiragBhalodia;https://www.youtube.com/watch?v=lNdy8HREvgo;License: Standard YouTube License, CC-BY