Assume that your cache has a 2% miss rate for instruction memory and a 4% miss rate for data memory. The miss penalty for instruction memory cache is 100 cycles and for data memory cache is 200 cycles. The base CPI is 1 cycle. Assume that you have a code that contains 200 instructions and 40% of them are load and store instructions, the rest of them are R type of arithmetic instruction. What is the total clock cycle to execute the code? Hint: The question is asking the TOTAL clock cycle, not average CPI

Assume that your cache has a 2% miss rate for instruction memory and a 4% miss rate for data memory. The miss penalty for instruction memory cache is 100 cycles and for data memory cache is 200 cycles. The base CPI is 1 cycle. Assume that you have a code that contains 200 instructions and 40% of them are load and store instructions, the rest of them are R type of arithmetic instruction. What is the total clock cycle to execute the code? Hint: The question is asking the TOTAL clock cycle, not average CPI

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 15VE: A(n) ________________ instruction always alters the instruction execution sequence. A(n)...

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