Assembly code for Conditional jump: long absSum(long start, long count) start in %rdi, count in %rsi absSum: irmovq $8, %r8 irmovq $1, %r9 xorq %rax, %rax andq %rsi, %rsi jmp test loop: mrmovq (%rdi),%r10 xorq %r11, %r11 subq %r10, %r11 jle pos rrmovq %r11, %r10 pos: addq %r10, %rax addq %r8, %rdi subq %r9, %rsi test: jne loop ret Assembly code for Conditional move: long absSum(long start, long count) start in %rdi, count in %rsi absSum: irmovq $8, %r8 irmovq $1, %r9 xorq %rax, %rax andq %rsi, %rsi jmp test loop: mrmovq (%rdi),%r10 xorq %r11, %r11 subq %r10, %r11 cmovg %r11, %r10 addq %r10, %rax addq %r8, %rdi subq %r9, %rsi test: jne loop ret Processing stages: The processing of an instruction has number of operations. The operations are organized into particular sequence of stages. It attempts to follow a uniform sequence for all instructions. The description of stages are shown below: Fetch: It uses program counter “PC” as memory address to read instruction bytes from memory. The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction. It fetches “valC” that denotes an 8-byte constant. It computes “valP” that denotes value of “PC” plus length of fetched instruction. Decode: The register file is been read with two operands. It gives values “valA” and “valB” for operands. It reads registers with instruction fields “rA” and “rB”. Execute: In this stage the ALU either performs required operation or increments and decrements stack pointer. The resulting value is termed as “valE”. The condition codes are evaluated and destination register is updated based on condition. It determines whether branch should be taken or not in a jump instruction. Memory: The data is been written to memory or read from memory in this stage. The value that is read is determined as “valM”. Write back: The results are been written to register file. It can write up to two results. PC update: The program counter “PC” denotes memory address to read bytes of instruction from memory. It is used to set next instruction’s address.

Question

Want to see the full answer?

Answer 1

Question

Chapter 4.5, Problem 4.44PP

A.

Program Plan Intro

Assembly code for Conditional jump:

long absSum(long start, long count)

start in %rdi, count in %rsi

absSum:

irmovq $8, %r8

irmovq $1, %r9

xorq %rax, %rax

andq %rsi, %rsi

jmp test

loop:

mrmovq (%rdi),%r10

xorq %r11, %r11

subq %r10, %r11

jle pos

rrmovq %r11, %r10

pos:

addq %r10, %rax

addq %r8, %rdi

subq %r9, %rsi

test:

jne loop

ret

Assembly code for Conditional move:

long absSum(long start, long count)

start in %rdi, count in %rsi

absSum:

irmovq $8, %r8

irmovq $1, %r9

xorq %rax, %rax

andq %rsi, %rsi

jmp test

loop:

mrmovq (%rdi),%r10

xorq %r11, %r11

subq %r10, %r11

cmovg %r11, %r10

addq %r10, %rax

addq %r8, %rdi

subq %r9, %rsi

test:

jne loop

ret

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

B.

Program Plan Intro

Assembly code for Conditional jump:

long absSum(long start, long count)

start in %rdi, count in %rsi

absSum:

irmovq $8, %r8

irmovq $1, %r9

xorq %rax, %rax

andq %rsi, %rsi

jmp test

loop:

mrmovq (%rdi),%r10

xorq %r11, %r11

subq %r10, %r11

jle pos

rrmovq %r11, %r10

pos:

addq %r10, %rax

addq %r8, %rdi

subq %r9, %rsi

test:

jne loop

ret

Assembly code for Conditional move:

long absSum(long start, long count)

start in %rdi, count in %rsi

absSum:

irmovq $8, %r8

irmovq $1, %r9

xorq %rax, %rax

andq %rsi, %rsi

jmp test

loop:

mrmovq (%rdi),%r10

xorq %r11, %r11

subq %r10, %r11

cmovg %r11, %r10

addq %r10, %rax

addq %r8, %rdi

subq %r9, %rsi

test:

jne loop

ret

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

C.

Program Plan Intro

Assembly code for Conditional jump:

long absSum(long start, long count)

start in %rdi, count in %rsi

absSum:

irmovq $8, %r8

irmovq $1, %r9

xorq %rax, %rax

andq %rsi, %rsi

jmp test

loop:

mrmovq (%rdi),%r10

xorq %r11, %r11

subq %r10, %r11

jle pos

rrmovq %r11, %r10

pos:

addq %r10, %rax

addq %r8, %rdi

subq %r9, %rsi

test:

jne loop

ret

Assembly code for Conditional move:

long absSum(long start, long count)

start in %rdi, count in %rsi

absSum:

irmovq $8, %r8

irmovq $1, %r9

xorq %rax, %rax

andq %rsi, %rsi

jmp test

loop:

mrmovq (%rdi),%r10

xorq %r11, %r11

subq %r10, %r11

cmovg %r11, %r10

addq %r10, %rax

addq %r8, %rdi

subq %r9, %rsi

test:

jne loop

ret

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

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f. Suppose that we are developing a new version of the AMD Barcelona processor with a 4 GHz clock rate. We have added some additional instructions to the instruction set in such a way that the number instructions has been reduced by 15%. The execution time is reduced to 700 s and the new SPECratio is 13.7. Find the new CPI. Ans. 1.37 g. This CPI value is larger than obtained in (a) as the clock rate was increased from 3 GHz to 4 GHz. Determine whether the increase in the CPI is similar to that of the clock rate. If they are dissimilar, why? Ans. 1.33, 1.45 h. By how much has the CPU time been reduced? Ans. 6.7% i. For a second benchmark, libquantum, assume an execution time of 960 ns, CPI of 1.61, and clock rate of 3 GHz. If the execution time is reduced by an additional 10% without affecting the CPI and with a clock rate of 4 GHz, determine the number of instructions. Ans. 2146 j. Determine the clock rate required to give a further 10% reduction in CPU time while maintaining the…

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Answer 2

Question

Chapter 4.5, Problem 4.44PP

A.

Program Plan Intro

Assembly code for Conditional jump:

long absSum(long start, long count)

start in %rdi, count in %rsi

absSum:

irmovq $8, %r8

irmovq $1, %r9

xorq %rax, %rax

andq %rsi, %rsi

jmp test

loop:

mrmovq (%rdi),%r10

xorq %r11, %r11

subq %r10, %r11

jle pos

rrmovq %r11, %r10

pos:

addq %r10, %rax

addq %r8, %rdi

subq %r9, %rsi

test:

jne loop

ret

Assembly code for Conditional move:

long absSum(long start, long count)

start in %rdi, count in %rsi

absSum:

irmovq $8, %r8

irmovq $1, %r9

xorq %rax, %rax

andq %rsi, %rsi

jmp test

loop:

mrmovq (%rdi),%r10

xorq %r11, %r11

subq %r10, %r11

cmovg %r11, %r10

addq %r10, %rax

addq %r8, %rdi

subq %r9, %rsi

test:

jne loop

ret

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

B.

Program Plan Intro

Assembly code for Conditional jump:

long absSum(long start, long count)

start in %rdi, count in %rsi

absSum:

irmovq $8, %r8

irmovq $1, %r9

xorq %rax, %rax

andq %rsi, %rsi

jmp test

loop:

mrmovq (%rdi),%r10

xorq %r11, %r11

subq %r10, %r11

jle pos

rrmovq %r11, %r10

pos:

addq %r10, %rax

addq %r8, %rdi

subq %r9, %rsi

test:

jne loop

ret

Assembly code for Conditional move:

long absSum(long start, long count)

start in %rdi, count in %rsi

absSum:

irmovq $8, %r8

irmovq $1, %r9

xorq %rax, %rax

andq %rsi, %rsi

jmp test

loop:

mrmovq (%rdi),%r10

xorq %r11, %r11

subq %r10, %r11

cmovg %r11, %r10

addq %r10, %rax

addq %r8, %rdi

subq %r9, %rsi

test:

jne loop

ret

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

C.

Program Plan Intro

Assembly code for Conditional jump:

long absSum(long start, long count)

start in %rdi, count in %rsi

absSum:

irmovq $8, %r8

irmovq $1, %r9

xorq %rax, %rax

andq %rsi, %rsi

jmp test

loop:

mrmovq (%rdi),%r10

xorq %r11, %r11

subq %r10, %r11

jle pos

rrmovq %r11, %r10

pos:

addq %r10, %rax

addq %r8, %rdi

subq %r9, %rsi

test:

jne loop

ret

Assembly code for Conditional move:

long absSum(long start, long count)

start in %rdi, count in %rsi

absSum:

irmovq $8, %r8

irmovq $1, %r9

xorq %rax, %rax

andq %rsi, %rsi

jmp test

loop:

mrmovq (%rdi),%r10

xorq %r11, %r11

subq %r10, %r11

cmovg %r11, %r10

addq %r10, %rax

addq %r8, %rdi

subq %r9, %rsi

test:

jne loop

ret

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

Expert Solution & Answer

Want to see the full answer?

Check out a sample textbook solution

See solution

Answer 3

Question

Chapter 4.5, Problem 4.44PP

A.

Program Plan Intro

Assembly code for Conditional jump:

long absSum(long start, long count)

start in %rdi, count in %rsi

absSum:

irmovq $8, %r8

irmovq $1, %r9

xorq %rax, %rax

andq %rsi, %rsi

jmp test

loop:

mrmovq (%rdi),%r10

xorq %r11, %r11

subq %r10, %r11

jle pos

rrmovq %r11, %r10

pos:

addq %r10, %rax

addq %r8, %rdi

subq %r9, %rsi

test:

jne loop

ret

Assembly code for Conditional move:

long absSum(long start, long count)

start in %rdi, count in %rsi

absSum:

irmovq $8, %r8

irmovq $1, %r9

xorq %rax, %rax

andq %rsi, %rsi

jmp test

loop:

mrmovq (%rdi),%r10

xorq %r11, %r11

subq %r10, %r11

cmovg %r11, %r10

addq %r10, %rax

addq %r8, %rdi

subq %r9, %rsi

test:

jne loop

ret

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

B.

Program Plan Intro

Assembly code for Conditional jump:

long absSum(long start, long count)

start in %rdi, count in %rsi

absSum:

irmovq $8, %r8

irmovq $1, %r9

xorq %rax, %rax

andq %rsi, %rsi

jmp test

loop:

mrmovq (%rdi),%r10

xorq %r11, %r11

subq %r10, %r11

jle pos

rrmovq %r11, %r10

pos:

addq %r10, %rax

addq %r8, %rdi

subq %r9, %rsi

test:

jne loop

ret

Assembly code for Conditional move:

long absSum(long start, long count)

start in %rdi, count in %rsi

absSum:

irmovq $8, %r8

irmovq $1, %r9

xorq %rax, %rax

andq %rsi, %rsi

jmp test

loop:

mrmovq (%rdi),%r10

xorq %r11, %r11

subq %r10, %r11

cmovg %r11, %r10

addq %r10, %rax

addq %r8, %rdi

subq %r9, %rsi

test:

jne loop

ret

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

C.

Program Plan Intro

Assembly code for Conditional jump:

long absSum(long start, long count)

start in %rdi, count in %rsi

absSum:

irmovq $8, %r8

irmovq $1, %r9

xorq %rax, %rax

andq %rsi, %rsi

jmp test

loop:

mrmovq (%rdi),%r10

xorq %r11, %r11

subq %r10, %r11

jle pos

rrmovq %r11, %r10

pos:

addq %r10, %rax

addq %r8, %rdi

subq %r9, %rsi

test:

jne loop

ret

Assembly code for Conditional move:

long absSum(long start, long count)

start in %rdi, count in %rsi

absSum:

irmovq $8, %r8

irmovq $1, %r9

xorq %rax, %rax

andq %rsi, %rsi

jmp test

loop:

mrmovq (%rdi),%r10

xorq %r11, %r11

subq %r10, %r11

cmovg %r11, %r10

addq %r10, %rax

addq %r8, %rdi

subq %r9, %rsi

test:

jne loop

ret

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

Expert Solution & Answer

Want to see the full answer?

Check out a sample textbook solution

See solution

Answer 4

Question

Chapter 4.5, Problem 4.44PP

A.

Program Plan Intro

Assembly code for Conditional jump:

long absSum(long start, long count)

start in %rdi, count in %rsi

absSum:

irmovq $8, %r8

irmovq $1, %r9

xorq %rax, %rax

andq %rsi, %rsi

jmp test

loop:

mrmovq (%rdi),%r10

xorq %r11, %r11

subq %r10, %r11

jle pos

rrmovq %r11, %r10

pos:

addq %r10, %rax

addq %r8, %rdi

subq %r9, %rsi

test:

jne loop

ret

Assembly code for Conditional move:

long absSum(long start, long count)

start in %rdi, count in %rsi

absSum:

irmovq $8, %r8

irmovq $1, %r9

xorq %rax, %rax

andq %rsi, %rsi

jmp test

loop:

mrmovq (%rdi),%r10

xorq %r11, %r11

subq %r10, %r11

cmovg %r11, %r10

addq %r10, %rax

addq %r8, %rdi

subq %r9, %rsi

test:

jne loop

ret

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

B.

Program Plan Intro

Assembly code for Conditional jump:

long absSum(long start, long count)

start in %rdi, count in %rsi

absSum:

irmovq $8, %r8

irmovq $1, %r9

xorq %rax, %rax

andq %rsi, %rsi

jmp test

loop:

mrmovq (%rdi),%r10

xorq %r11, %r11

subq %r10, %r11

jle pos

rrmovq %r11, %r10

pos:

addq %r10, %rax

addq %r8, %rdi

subq %r9, %rsi

test:

jne loop

ret

Assembly code for Conditional move:

long absSum(long start, long count)

start in %rdi, count in %rsi

absSum:

irmovq $8, %r8

irmovq $1, %r9

xorq %rax, %rax

andq %rsi, %rsi

jmp test

loop:

mrmovq (%rdi),%r10

xorq %r11, %r11

subq %r10, %r11

cmovg %r11, %r10

addq %r10, %rax

addq %r8, %rdi

subq %r9, %rsi

test:

jne loop

ret

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

C.

Program Plan Intro

Assembly code for Conditional jump:

long absSum(long start, long count)

start in %rdi, count in %rsi

absSum:

irmovq $8, %r8

irmovq $1, %r9

xorq %rax, %rax

andq %rsi, %rsi

jmp test

loop:

mrmovq (%rdi),%r10

xorq %r11, %r11

subq %r10, %r11

jle pos

rrmovq %r11, %r10

pos:

addq %r10, %rax

addq %r8, %rdi

subq %r9, %rsi

test:

jne loop

ret

Assembly code for Conditional move:

long absSum(long start, long count)

start in %rdi, count in %rsi

absSum:

irmovq $8, %r8

irmovq $1, %r9

xorq %rax, %rax

andq %rsi, %rsi

jmp test

loop:

mrmovq (%rdi),%r10

xorq %r11, %r11

subq %r10, %r11

cmovg %r11, %r10

addq %r10, %rax

addq %r8, %rdi

subq %r9, %rsi

test:

jne loop

ret

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

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Answer 5

Chapter 4.5, Problem 4.44PP

A.

Program Plan Intro

Assembly code for Conditional jump:

long absSum(long start, long count)

start in %rdi, count in %rsi

absSum:

irmovq $8, %r8

irmovq $1, %r9

xorq %rax, %rax

andq %rsi, %rsi

jmp test

loop:

mrmovq (%rdi),%r10

xorq %r11, %r11

subq %r10, %r11

jle pos

rrmovq %r11, %r10

pos:

addq %r10, %rax

addq %r8, %rdi

subq %r9, %rsi

test:

jne loop

ret

Assembly code for Conditional move:

long absSum(long start, long count)

start in %rdi, count in %rsi

absSum:

irmovq $8, %r8

irmovq $1, %r9

xorq %rax, %rax

andq %rsi, %rsi

jmp test

loop:

mrmovq (%rdi),%r10

xorq %r11, %r11

subq %r10, %r11

cmovg %r11, %r10

addq %r10, %rax

addq %r8, %rdi

subq %r9, %rsi

test:

jne loop

ret

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

B.

Program Plan Intro

Assembly code for Conditional jump:

long absSum(long start, long count)

start in %rdi, count in %rsi

absSum:

irmovq $8, %r8

irmovq $1, %r9

xorq %rax, %rax

andq %rsi, %rsi

jmp test

loop:

mrmovq (%rdi),%r10

xorq %r11, %r11

subq %r10, %r11

jle pos

rrmovq %r11, %r10

pos:

addq %r10, %rax

addq %r8, %rdi

subq %r9, %rsi

test:

jne loop

ret

Assembly code for Conditional move:

long absSum(long start, long count)

start in %rdi, count in %rsi

absSum:

irmovq $8, %r8

irmovq $1, %r9

xorq %rax, %rax

andq %rsi, %rsi

jmp test

loop:

mrmovq (%rdi),%r10

xorq %r11, %r11

subq %r10, %r11

cmovg %r11, %r10

addq %r10, %rax

addq %r8, %rdi

subq %r9, %rsi

test:

jne loop

ret

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

C.

Program Plan Intro

Assembly code for Conditional jump:

long absSum(long start, long count)

start in %rdi, count in %rsi

absSum:

irmovq $8, %r8

irmovq $1, %r9

xorq %rax, %rax

andq %rsi, %rsi

jmp test

loop:

mrmovq (%rdi),%r10

xorq %r11, %r11

subq %r10, %r11

jle pos

rrmovq %r11, %r10

pos:

addq %r10, %rax

addq %r8, %rdi

subq %r9, %rsi

test:

jne loop

ret

Assembly code for Conditional move:

long absSum(long start, long count)

start in %rdi, count in %rsi

absSum:

irmovq $8, %r8

irmovq $1, %r9

xorq %rax, %rax

andq %rsi, %rsi

jmp test

loop:

mrmovq (%rdi),%r10

xorq %r11, %r11

subq %r10, %r11

cmovg %r11, %r10

addq %r10, %rax

addq %r8, %rdi

subq %r9, %rsi

test:

jne loop

ret

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

Answer 6

Chapter 4.5, Problem 4.44PP

A.

Program Plan Intro

Assembly code for Conditional jump:

long absSum(long start, long count)

start in %rdi, count in %rsi

absSum:

irmovq $8, %r8

irmovq $1, %r9

xorq %rax, %rax

andq %rsi, %rsi

jmp test

loop:

mrmovq (%rdi),%r10

xorq %r11, %r11

subq %r10, %r11

jle pos

rrmovq %r11, %r10

pos:

addq %r10, %rax

addq %r8, %rdi

subq %r9, %rsi

test:

jne loop

ret

Assembly code for Conditional move:

long absSum(long start, long count)

start in %rdi, count in %rsi

absSum:

irmovq $8, %r8

irmovq $1, %r9

xorq %rax, %rax

andq %rsi, %rsi

jmp test

loop:

mrmovq (%rdi),%r10

xorq %r11, %r11

subq %r10, %r11

cmovg %r11, %r10

addq %r10, %rax

addq %r8, %rdi

subq %r9, %rsi

test:

jne loop

ret

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

Answer 7

Chapter 4.5, Problem 4.44PP

A.

Program Plan Intro

Assembly code for Conditional jump:

long absSum(long start, long count)

start in %rdi, count in %rsi

absSum:

irmovq $8, %r8

irmovq $1, %r9

xorq %rax, %rax

andq %rsi, %rsi

jmp test

loop:

mrmovq (%rdi),%r10

xorq %r11, %r11

subq %r10, %r11

jle pos

rrmovq %r11, %r10

pos:

addq %r10, %rax

addq %r8, %rdi

subq %r9, %rsi

test:

jne loop

ret

Assembly code for Conditional move:

long absSum(long start, long count)

start in %rdi, count in %rsi

absSum:

irmovq $8, %r8

irmovq $1, %r9

xorq %rax, %rax

andq %rsi, %rsi

jmp test

loop:

mrmovq (%rdi),%r10

xorq %r11, %r11

subq %r10, %r11

cmovg %r11, %r10

addq %r10, %rax

addq %r8, %rdi

subq %r9, %rsi

test:

jne loop

ret

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

Answer 8

B.

Program Plan Intro

Assembly code for Conditional jump:

long absSum(long start, long count)

start in %rdi, count in %rsi

absSum:

irmovq $8, %r8

irmovq $1, %r9

xorq %rax, %rax

andq %rsi, %rsi

jmp test

loop:

mrmovq (%rdi),%r10

xorq %r11, %r11

subq %r10, %r11

jle pos

rrmovq %r11, %r10

pos:

addq %r10, %rax

addq %r8, %rdi

subq %r9, %rsi

test:

jne loop

ret

Assembly code for Conditional move:

long absSum(long start, long count)

start in %rdi, count in %rsi

absSum:

irmovq $8, %r8

irmovq $1, %r9

xorq %rax, %rax

andq %rsi, %rsi

jmp test

loop:

mrmovq (%rdi),%r10

xorq %r11, %r11

subq %r10, %r11

cmovg %r11, %r10

addq %r10, %rax

addq %r8, %rdi

subq %r9, %rsi

test:

jne loop

ret

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

Answer 9

B.

Program Plan Intro

Assembly code for Conditional jump:

long absSum(long start, long count)

start in %rdi, count in %rsi

absSum:

irmovq $8, %r8

irmovq $1, %r9

xorq %rax, %rax

andq %rsi, %rsi

jmp test

loop:

mrmovq (%rdi),%r10

xorq %r11, %r11

subq %r10, %r11

jle pos

rrmovq %r11, %r10

pos:

addq %r10, %rax

addq %r8, %rdi

subq %r9, %rsi

test:

jne loop

ret

Assembly code for Conditional move:

long absSum(long start, long count)

start in %rdi, count in %rsi

absSum:

irmovq $8, %r8

irmovq $1, %r9

xorq %rax, %rax

andq %rsi, %rsi

jmp test

loop:

mrmovq (%rdi),%r10

xorq %r11, %r11

subq %r10, %r11

cmovg %r11, %r10

addq %r10, %rax

addq %r8, %rdi

subq %r9, %rsi

test:

jne loop

ret

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

Answer 10

C.

Program Plan Intro

Assembly code for Conditional jump:

long absSum(long start, long count)

start in %rdi, count in %rsi

absSum:

irmovq $8, %r8

irmovq $1, %r9

xorq %rax, %rax

andq %rsi, %rsi

jmp test

loop:

mrmovq (%rdi),%r10

xorq %r11, %r11

subq %r10, %r11

jle pos

rrmovq %r11, %r10

pos:

addq %r10, %rax

addq %r8, %rdi

subq %r9, %rsi

test:

jne loop

ret

Assembly code for Conditional move:

long absSum(long start, long count)

start in %rdi, count in %rsi

absSum:

irmovq $8, %r8

irmovq $1, %r9

xorq %rax, %rax

andq %rsi, %rsi

jmp test

loop:

mrmovq (%rdi),%r10

xorq %r11, %r11

subq %r10, %r11

cmovg %r11, %r10

addq %r10, %rax

addq %r8, %rdi

subq %r9, %rsi

test:

jne loop

ret

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

Answer 11

C.

Program Plan Intro

Assembly code for Conditional jump:

long absSum(long start, long count)

start in %rdi, count in %rsi

absSum:

irmovq $8, %r8

irmovq $1, %r9

xorq %rax, %rax

andq %rsi, %rsi

jmp test

loop:

mrmovq (%rdi),%r10

xorq %r11, %r11

subq %r10, %r11

jle pos

rrmovq %r11, %r10

pos:

addq %r10, %rax

addq %r8, %rdi

subq %r9, %rsi

test:

jne loop

ret

Assembly code for Conditional move:

long absSum(long start, long count)

start in %rdi, count in %rsi

absSum:

irmovq $8, %r8

irmovq $1, %r9

xorq %rax, %rax

andq %rsi, %rsi

jmp test

loop:

mrmovq (%rdi),%r10

xorq %r11, %r11

subq %r10, %r11

cmovg %r11, %r10

addq %r10, %rax

addq %r8, %rdi

subq %r9, %rsi

test:

jne loop

ret

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

Answer 12

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Answer 13

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Answer 14

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Answer 15

Ch. 4.1 - Prob. 4.1PP Ch. 4.1 - Prob. 4.2PP Ch. 4.1 - Prob. 4.3PP Ch. 4.1 - Prob. 4.4PP Ch. 4.1 - Prob. 4.5PP Ch. 4.1 - Prob. 4.6PP Ch. 4.1 - Prob. 4.7PP Ch. 4.1 - Prob. 4.8PP Ch. 4.2 - Practice Problem 4.9 (solution page 484) Write an...Ch. 4.2 - Prob. 4.10PP

Solution Summary: The author explains the assembly code for Conditional jump: long absSum(long *start, long count) start in %rdi, count in

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