Computer Systems: A Programmer's Perspective (3rd Edition)
3rd Edition
ISBN: 9780134092669
Author: Bryant, Randal E. Bryant, David R. O'Hallaron, David R., Randal E.; O'Hallaron, Bryant/O'hallaron
Publisher: PEARSON
expand_more
expand_more
format_list_bulleted
Question
Chapter 4.3, Problem 4.17PP
Program Plan Intro
Processing stages:
- The processing of an instruction has number of operations.
- The operations are organized into particular sequence of stages.
- It attempts to follow a uniform sequence for all instructions.
- The description of stages are shown below:
- Fetch:
- It uses program counter “PC” as memory address to read instruction bytes from memory.
- The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.
- It fetches “valC” that denotes an 8-byte constant.
- It computes “valP” that denotes value of “PC” plus length of fetched instruction.
- Decode:
- The register file is been read with two operands.
- It gives values “valA” and “valB” for operands.
- It reads registers with instruction fields “rA” and “rB”.
- Execute:
- In this stage the ALU either performs required operation or increments and decrements stack pointer.
- The resulting value is termed as “valE”.
- The condition codes are evaluated and destination register is updated based on condition.
- It determines whether branch should be taken or not in a jump instruction.
- Memory:
- The data is been written to memory or read from memory in this stage.
- The value that is read is determined as “valM”.
- Write back:
- The results are been written to register file.
- It can write up to two results.
- PC update:
- The program counter “PC” denotes memory address to read bytes of instruction from memory.
- It is used to set next instruction’s address.
- Fetch:
Expert Solution & Answer
Want to see the full answer?
Check out a sample textbook solutionStudents have asked these similar questions
2. [4pts] Use the following C-Code for the problems below.
int recFunc (int a, int b) {
if (b
= 0)
==
return a;
else
return 1+recFunc (a, b-1);
a. Give the flowchart for the C-Code
b. Convert to MIPS assembly and comment each assembly instruction to indicate
corresponding C-Code.
Q2. Refer to datapath design on slide no. 26 with added blocks for jump instructions as shown inslide 33 in Chapter 4 (part 1). Let’s assume a program has 500 instructions. These instructions aredistributed as follows:R-Type Immediatearithmetic(addi)Load Store Branch Jump25% 5% 20% 20% 10% 20%Answer the following questions (show calculations):a) How many instructions will use instruction memory?b) How many instructions will use data memory?c) How many instructions will use the sign extend block?d) In the clock cycles, where the sign extend block is not required, does it remain idle? If yes,how? If not, what happens to the output of the block in that cycle?
chapter 4, slide 33 is added as an image needed to solve the question
Computer Science
Consider the following comparison instruction:TST R0, R1, ASR #1 ; R0 = 0x12345678 and R1 = 0xDB97530F(i) Appraise the value of the condition flags (N, Z, C, V) after the execution of the instruction. Use the values of R0 and R1 provided in the instruction comment.(ii) The conditional branches are BHS, BLO, BLT and BPL. From the condition flag bits appraised in Question 2(b)(i), determine which of the above conditional branches will be executed.
Chapter 4 Solutions
Computer Systems: A Programmer's Perspective (3rd Edition)
Ch. 4.1 - Prob. 4.1PPCh. 4.1 - Prob. 4.2PPCh. 4.1 - Prob. 4.3PPCh. 4.1 - Prob. 4.4PPCh. 4.1 - Prob. 4.5PPCh. 4.1 - Prob. 4.6PPCh. 4.1 - Prob. 4.7PPCh. 4.1 - Prob. 4.8PPCh. 4.2 - Practice Problem 4.9 (solution page 484) Write an...Ch. 4.2 - Prob. 4.10PP
Ch. 4.2 - Prob. 4.11PPCh. 4.2 - Prob. 4.12PPCh. 4.3 - Prob. 4.13PPCh. 4.3 - Prob. 4.14PPCh. 4.3 - Prob. 4.15PPCh. 4.3 - Prob. 4.16PPCh. 4.3 - Prob. 4.17PPCh. 4.3 - Prob. 4.18PPCh. 4.3 - Prob. 4.19PPCh. 4.3 - Prob. 4.20PPCh. 4.3 - Prob. 4.21PPCh. 4.3 - Prob. 4.22PPCh. 4.3 - Prob. 4.23PPCh. 4.3 - Prob. 4.24PPCh. 4.3 - Prob. 4.25PPCh. 4.3 - Prob. 4.26PPCh. 4.3 - Prob. 4.27PPCh. 4.4 - Prob. 4.28PPCh. 4.4 - Prob. 4.29PPCh. 4.5 - Prob. 4.30PPCh. 4.5 - Prob. 4.31PPCh. 4.5 - Prob. 4.32PPCh. 4.5 - Prob. 4.33PPCh. 4.5 - Prob. 4.34PPCh. 4.5 - Prob. 4.35PPCh. 4.5 - Prob. 4.36PPCh. 4.5 - Prob. 4.37PPCh. 4.5 - Prob. 4.38PPCh. 4.5 - Prob. 4.39PPCh. 4.5 - Prob. 4.40PPCh. 4.5 - Prob. 4.41PPCh. 4.5 - Prob. 4.42PPCh. 4.5 - Prob. 4.43PPCh. 4.5 - Prob. 4.44PPCh. 4 - Prob. 4.45HWCh. 4 - Prob. 4.46HWCh. 4 - Prob. 4.47HWCh. 4 - Prob. 4.48HWCh. 4 - Modify the code you wrote for Problem 4.47 to...Ch. 4 - In Section 3.6.8, we saw that a common way to...Ch. 4 - Prob. 4.51HWCh. 4 - The file seq-full.hcl contains the HCL description...Ch. 4 - Prob. 4.53HWCh. 4 - The file pie=full. hcl contains a copy of the PIPE...Ch. 4 - Prob. 4.55HWCh. 4 - Prob. 4.56HWCh. 4 - Prob. 4.57HWCh. 4 - Our pipelined design is a bit unrealistic in that...Ch. 4 - Prob. 4.59HW
Knowledge Booster
Similar questions
- a) b) Explain the following machine independent optimization techniques. Common sub expression and dead code elimination Copy propagation, constant folding. Instruction scheduling.arrow_forwardQ2) Answer the following sentence with (True) or (False) and correct the false answer: (20 Marks) 1. CMPS is used with REPE, REPZ, REPNE and REPNZ. 2. Loop instruction is equal to JNZ instruction. 3. SAL and SHL have the same operation. 4. The instruction MOV BX,'B' is allowed. 5. Segment override prefix means we can use any segment register to have the physical address. 6. In CBW, the MSB of AX is copied to all the bits in DX. 7. The following piece of code is used to: Complement PF and CF LAHF AND AH, FOH XOR AH, OFH SAHF 8. In conditional jump, the next instruction is executed if the condition is not met. 9. Assume BL=11H, AX=FFB6 H, the result of executing IDIV BL is AX=FAFD H 10. The instruction queue in the BIU works on LIFO basis.arrow_forwardQ41 (a) Generate a full RTN code in Fetch, Decode, Execute and Write Back step for: MUL 602, #5, #2 Assume that, in this instruction, the registers used to temporarily store the fetched data are R1 and R2. The result of arithmetic operation is stored temporarily in R3 before it being stored back in memory location M[602]. The initial Program Counter value is 500. The illustration is as in Figure Q41(a). Memory CPU Register 500 0600 0500 PC 501 0601 IR R1 R2 600 0005 R3 601 0003 602 Figure Q41(a)arrow_forward
- [2] ( Explain for each line why you chose a certain suffix such as b,w,l or q For each of the following lines of assembly language, determine the appropriate instruction suffix based on the operands. (For example, mov can be rewritten as movb, movw, movl, or movq.) mov mov mov που mov mov %oax, (%rsp) (%rax), %dx $0xFF, %bl (%rap,%rdx, 4), %d1 %rdx), %rax %dx, (%rax)arrow_forwardc) Instruction j Label is stored at 0x00400030, and Label is at instruction address 0x00400050. Encode this instruction and express your answer in hexadecimal. The opcode for the jump instruction is 000010. Answer: 08100014 d) We would like to load into register $s1 the decimal value 131077 (Note that 131072 = - 21"). Write a sequence of MIPS instructions to do that. Answer: lui $s2, 2 ori Ss2, $s2, 5arrow_forwardQuestion 3 Execute the following instruction by the following SS and show the execution of A- Inorder Issue & In Order Completion B- Inorder Issue & Out of Order Completion Div / ADD / Sw Mul F0 , F2 , F4 Add F9 , F10 , FO Div F9, F23 , F25 Sub F19 , F15 , F9 Div F44 , F25 , F90 Sw F0 , 5(R1) Sub F13, F15 , F16 ai a2 a3 f1 di Other f2 d2 S2 elarrow_forward
- [2] ( Explain for each line why you chose a certain suffix such as b,w,l or q For each of the following lines of assembly language, determine the appropriate instruction suffix based on the operands. (For example, mov can be rewritten as movb, movw, movl, or movq.) mov mov mov που mov που Zeax, (%rap) (%rax), %dx $0xFF, %bl (%rap,%rdx, 4), %d1 (%rdx), %rax %dx, (%rax)arrow_forward[1] ( Show your work. Show hoe you compute memory address by using the effective memory address computation. Assume the following values are stored at the indicated memory addresses and registers: Address Value 0x100 OxFF 0x104 OxAB 0x108 0x13 0x10c 0x11 Register %rax %rcx %rdx $0x108 (%rax) 4(%rax) 9(%rax, %rdx) 260(%rcx,%rdx) OxFC (,%rcx, 4) (%rax, %rdx, 4) Value 0x100 0x1 0x3 Fill in the following table showing the values for the indicated operands: Operand Value %rax 0x104arrow_forward(c) The following Sigma 16 program has been loaded into memory at address 0000: load R3,y[RO] load R4,x[RO] lea R5, 2[RO] sub R1,R4,R3 mul R2,R1,R5 store R2,w[RO] trap RO,RO,RO x data 10 y data 12 w data 0 Show the content of the memory writing hexadecimal representation and using a table with 3 columns: the memory address, the contents of that memory address, and an explanation of what "the content (of that memory address) means". As a reference, here are the opcodes for RRR instructions: add 0, sub 1, mul 2, trap c. And here the opcodes for RX instructions: lea 0, load 1, store 2. [7]arrow_forward
- Discussion 1- Explain what operation is performed by each of the instruction that follow a. MOV AX,0110H b. MOV DI ,AX c. MOV [100H],BX d. MOV [BX+DI],AX e. XCHG BX,DI f. MOV DX, 'AB'arrow_forwardDO any part if do able A Instruction Set Architecture A.1 Instruction set We present a list of instructions typical of a RISC (reduced instruction set computer) machine. In data-movement and control instructions, the addresses may be immediate #X, direct (memory) M, indirect (memory) [M], register r, or register indirect [r] addresses. Data-processing instructions use immediate or register addressing. PC is the programme counter and a <- b indicates that the value of b is placed in a. LOAD a, b a <- b STOR a, b a <- b ADD a, b, c a <- b + c ASH a, b, c a <- (b >>[s] c) LSH a, b, c a <- (b >>[u] c) BR a PC <- a SUB a, b, c a <- b - c BEQ a, b, c PC <- a if b = c MUL a, b, c a <- b * c BNE a, b, c PC <- a if not b = c DIV a, b, c a <-…arrow_forwardProblem I ( Assembler ) Provide the assembly implementation of the C - code below . Sub 10 is a function that subtract 10 from a given input x. Assumption : MyArray base address is store in register $S1. Feel free to use instruction li or si. li load an immediate value into a register . For instance, li $S4 5 will copy value 5 into register $S4. C code for ( i = 0,1 < 10 , i ++ ) { MyArray [ i ] = MyArray [ i - 1 ] + MyArray [ i + 1 ] ; Sub10 ( MyArray [ i ]; } Sub10 ( x ) { Return ( x - 10 ) ; } Code in Assembly Language: sub10(int): ; Implementation of the sub10() function push rbp mov rbp, rsp mov DWORD PTR [rbp-4], edi mov eax, DWORD PTR [rbp-4] sub eax, 10 pop rbp ret main: ; Main function Implementation push rbp mov rbp, rsp sub rsp, 64 mov…arrow_forward
arrow_back_ios
SEE MORE QUESTIONS
arrow_forward_ios
Recommended textbooks for you
- Database System ConceptsComputer ScienceISBN:9780078022159Author:Abraham Silberschatz Professor, Henry F. Korth, S. SudarshanPublisher:McGraw-Hill EducationStarting Out with Python (4th Edition)Computer ScienceISBN:9780134444321Author:Tony GaddisPublisher:PEARSONDigital Fundamentals (11th Edition)Computer ScienceISBN:9780132737968Author:Thomas L. FloydPublisher:PEARSON
- C How to Program (8th Edition)Computer ScienceISBN:9780133976892Author:Paul J. Deitel, Harvey DeitelPublisher:PEARSONDatabase Systems: Design, Implementation, & Manag...Computer ScienceISBN:9781337627900Author:Carlos Coronel, Steven MorrisPublisher:Cengage LearningProgrammable Logic ControllersComputer ScienceISBN:9780073373843Author:Frank D. PetruzellaPublisher:McGraw-Hill Education
Database System Concepts
Computer Science
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:McGraw-Hill Education
Starting Out with Python (4th Edition)
Computer Science
ISBN:9780134444321
Author:Tony Gaddis
Publisher:PEARSON
Digital Fundamentals (11th Edition)
Computer Science
ISBN:9780132737968
Author:Thomas L. Floyd
Publisher:PEARSON
C How to Program (8th Edition)
Computer Science
ISBN:9780133976892
Author:Paul J. Deitel, Harvey Deitel
Publisher:PEARSON
Database Systems: Design, Implementation, & Manag...
Computer Science
ISBN:9781337627900
Author:Carlos Coronel, Steven Morris
Publisher:Cengage Learning
Programmable Logic Controllers
Computer Science
ISBN:9780073373843
Author:Frank D. Petruzella
Publisher:McGraw-Hill Education