Chapter 13, Problem 13.33P

The CMOS op−amp in Figure 13.14 is biased at $V^{+}=5\text{V}$ and $V^{-}=-5\text{V}$ . Let $R_{\text{set}}=50\text{k}\Omega$ . Assume transistor parameters of $V_{TN}=0.7\text{V}$ , $V_{TP}=-0.7\text{V}$ , ${k^{\prime }}_n=100\mu {\text{A/V}}^{\text{2}}$ , ${k^{\prime }}_p=40\mu {\text{A/V}}^{\text{2}}$ , ${\lambda }_n=0.02{\text{V}}^{-1}$ , and ${\lambda }_p=0.04{\text{V}}^{-1}$ . The transistor width−to−length ratios are ${\left(W/L\right)}_{3,4}=15$ , ${\left(W/L\right)}_7=30$ , and $\left(W/L\right)=50$ for all other transistors. (a) Determine $I_{\text{set}},I_Q$ , and $I_{DQ7}$ . (b) Find the small−signal voltage gains of the input and second stages, and the overall voltage gain.