Programmable Logic Controllers
5th Edition
ISBN: 9780073373843
Author: Frank D. Petruzella
Publisher: McGraw-Hill Education
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Question
Chapter 7, Problem 9P
Program Plan Intro
Timer:
- Timer is mainly used to keep an output ON for a specific length of time.
- It provides a preset delay to the control actions.
- In a timer, the output will be energized when the preset value becomes equal to the accumulated value.
- Three different types of timers include a Delay-OFF, a Delay-ON, and a Delay-ON-Retentive timer.
Timer ON Delay (TON):
- TON refers to an on-delay timer.
- The on-delay timer is the most commonly used timer.
- TON counts the time-based intervals as soon as the instruction becomes true.
- Here, the output changes its state from low to high when the timer provides some time delay (instruction goes from OFF to ON state).
Explanation of Solution
b.
Given:
Consider the given conditions,
- Input = True
- EN = 1
- TT = 1
- DN = 1
Explanation:
The given program uses TON, so if the input is true, then the instruction will start to execute the program.
- The timer “T4:0” will start timing and the EN signal bits get activated.
- Next, the TT also turns into “true” until the accumulated values attains the preset value “10”...
Explanation of Solution
c.
Given:
Consider the given conditions,
- Input = False
- EN = 0
- TT = 0
- DN = 0
Explanation:
- The given program uses TON, so if the input is true, then the instruction will start to execute the program...
Explanation of Solution
d.
Given:
Consider the given conditions,
- Input = True
- EN = 1
- TT = 0
- DN = 1
Explanation:
The given program uses TON, so if the input is true, then the instruction will start to execute the program.
- The timer “T4:0” will start timing and the EN signal bits get activated...
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Students have asked these similar questions
Q1/ Estimate the Truth Table of the logic
circuit shown below and use it to draw the
timing diagram of the output signal X and Y
in proper relation to the inputs
A
::
Y
се
=
0,
Design a sequential circuit with two D flip-flops A and B, and one input x_in. When x_in
the state of the circuit remains the same. When x in = 1, the circuit goes through the state
transitions from 00 to 01, to 11, to 10, back to 00, and repeats.
A sequential circuit has three flip-flops A, B, C; one input, x; and one output y. The state diagram is shown in Fig. P6-22. The circuit is to be designed by treating the unused state as don't - care condition. The final circuit must be analyzed to ensure that it is self correcting.
(B) Use JK flip-flops in the design
Chapter 7 Solutions
Programmable Logic Controllers
Ch. 7 - Prob. 1RQCh. 7 - Prob. 2RQCh. 7 - Prob. 3RQCh. 7 - Prob. 4RQCh. 7 - a. What are the two methods commonly used to...Ch. 7 - Prob. 6RQCh. 7 - Prob. 7RQCh. 7 - Prob. 8RQCh. 7 - For a TOF timer: a. When is the enable bit of a...Ch. 7 - Explain what each of the following quantities...
Ch. 7 - State the method used to reset the accumulated...Ch. 7 - Study the ladder logic program in Figure 7-40 and...Ch. 7 - Study the ladder logic program in Figure 7-42, and...Ch. 7 - Prob. 6PCh. 7 - Prob. 7PCh. 7 - Prob. 8PCh. 7 - Prob. 9PCh. 7 - Prob. 10PCh. 7 - Prob. 11PCh. 7 - Prob. 13PCh. 7 - When the lights are turned off in a building, an...
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- IV. PROCEDURES: For the AND gate look on the data sheets, connect the circuit on Breadboard and test the gate. Using logic switches SW1 and SW2, apply the logic levels 0 and 1 to gate inputs Create a truth table and record the results Also simulate the given gate using the Circuit Wizard simulation software Obtain the corresponding circuit diagram using the simulation software of the Boolean expression F((A,B,C)= АВ* AC * ВС From the obtain circuit diagram develop the corresponding truth table From the figure below obtain the equivalent Boolean expression and develop its corresponding truth Table АП сПо- Boolean Expression: Z= (AB)(CD)arrow_forward2. Draw the timing diagram for the Clocked SR flip-flop at each of the instants t0 to t6 as described in the class meeting. a. at t0, Q is low, S is low, R is low b. at t0, Q is high, S is low, R is low Be sure to include the clock signal in the timing diagram.arrow_forwardDesign a logic circuit with input signal A, control input B, and outputs X and Y to operate as follows: When B = 1, output X will follow input A, and output Y will be 0. When B = 0, output X will be 0, and output Y will follow input A.arrow_forward
- Design circuit that has an input w and an output z. The circuit is a sequence detector that produces z = 1 when the previous two values of w were 00 or 11; otherwise z = 0. Use W=0101100010101110101011100010 a) For this problem design the circuit using JK flipflops, draw the state diagram, true table, logic circuit.b) Do the same that as part A but this time use D flipflops: draw the state diagram, true table, logic circuit.arrow_forwardDesigns a logic circuit that will allow a signal to pass to the output only when control inputs B and C are both HIGH; otherwise, the output will stay LOWarrow_forwardA sequential circuit has three flip-flops A, B, C; one input, x; and one output y. The state diagram is shown in Fig. P6-22. The circuit is to be designed by treating the unused state as don't - care condition. The final circuit must be analyzed to ensure that it is self correcting. (A) Use D flip-flops in the design(B) Use JK flip-flops in the designarrow_forward
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