Programmable Logic Controllers
5th Edition
ISBN: 9780073373843
Author: Frank D. Petruzella
Publisher: McGraw-Hill Education
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Question
Chapter 7, Problem 9P
Program Plan Intro
Timer:
- Timer is mainly used to keep an output ON for a specific length of time.
- It provides a preset delay to the control actions.
- In a timer, the output will be energized when the preset value becomes equal to the accumulated value.
- Three different types of timers include a Delay-OFF, a Delay-ON, and a Delay-ON-Retentive timer.
Timer ON Delay (TON):
- TON refers to an on-delay timer.
- The on-delay timer is the most commonly used timer.
- TON counts the time-based intervals as soon as the instruction becomes true.
- Here, the output changes its state from low to high when the timer provides some time delay (instruction goes from OFF to ON state).
Explanation of Solution
b.
Given:
Consider the given conditions,
- Input = True
- EN = 1
- TT = 1
- DN = 1
Explanation:
The given program uses TON, so if the input is true, then the instruction will start to execute the program.
- The timer “T4:0” will start timing and the EN signal bits get activated.
- Next, the TT also turns into “true” until the accumulated values attains the preset value “10”...
Explanation of Solution
c.
Given:
Consider the given conditions,
- Input = False
- EN = 0
- TT = 0
- DN = 0
Explanation:
- The given program uses TON, so if the input is true, then the instruction will start to execute the program...
Explanation of Solution
d.
Given:
Consider the given conditions,
- Input = True
- EN = 1
- TT = 0
- DN = 1
Explanation:
The given program uses TON, so if the input is true, then the instruction will start to execute the program.
- The timer “T4:0” will start timing and the EN signal bits get activated...
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Students have asked these similar questions
=
0,
Design a sequential circuit with two D flip-flops A and B, and one input x_in. When x_in
the state of the circuit remains the same. When x in = 1, the circuit goes through the state
transitions from 00 to 01, to 11, to 10, back to 00, and repeats.
Design a sequential circuit with two T flip-flops A and B and two inputs E and F and a
reset which will satisfy the following design requirements.
If E=0, the circuit remains in the same state regardless of the value of F.
When E=1 and F=1, the circuit goes through the state transitions from 00 to 01, to 10, to
11, back to 00, and repeats.
When E=1 and F=0, the circuit goes through the state transitions from 00 to 11, to 10, to
01, back to 00, and repeats.
The results should be consistent with the simulation timing diagrams shown below.
1. Draw a state diagram for this requirement using the template below.
2. Draw a present state / next state table for this requirement using the template
below.
3. Use Karnaugh maps to determine the flip flop minimized Boolean input
expressions.
4. Model the design requirement using Verilog structural source code. Use T flip-
flops. Provide the source code.
5. Simulate the structural model using a test bench with stimulus test signals as
shown in the…
IV. PROCEDURES:
For the AND gate look on the data sheets, connect the circuit on Breadboard and test the gate.
Using logic switches SW1 and SW2, apply the logic levels 0 and 1 to gate inputs
Create a truth table and record the results
Also simulate the given gate using the Circuit Wizard simulation software
Obtain the corresponding circuit diagram using the simulation software of the Boolean expression
F((A,B,C)=
АВ* AC * ВС
From the obtain circuit diagram develop the corresponding truth table
From the figure below obtain the equivalent Boolean expression and develop its corresponding truth Table
АП
сПо-
Boolean Expression:
Z= (AB)(CD)
Chapter 7 Solutions
Programmable Logic Controllers
Ch. 7 - Prob. 1RQCh. 7 - Prob. 2RQCh. 7 - Prob. 3RQCh. 7 - Prob. 4RQCh. 7 - a. What are the two methods commonly used to...Ch. 7 - Prob. 6RQCh. 7 - Prob. 7RQCh. 7 - Prob. 8RQCh. 7 - For a TOF timer: a. When is the enable bit of a...Ch. 7 - Explain what each of the following quantities...
Ch. 7 - State the method used to reset the accumulated...Ch. 7 - Study the ladder logic program in Figure 7-40 and...Ch. 7 - Study the ladder logic program in Figure 7-42, and...Ch. 7 - Prob. 6PCh. 7 - Prob. 7PCh. 7 - Prob. 8PCh. 7 - Prob. 9PCh. 7 - Prob. 10PCh. 7 - Prob. 11PCh. 7 - Prob. 13PCh. 7 - When the lights are turned off in a building, an...
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Need a deep-dive on the concept behind this application? Look no further. Learn more about this topic, computer-science and related others by exploring similar questions and additional content below.Similar questions
- Given the input for a negative level clocked D Flip-flop, draw the output timing diagram and answer the following questions. Assume that initially, the value of output is 0 (zero). Write: A - if the output is a high logic level B - if the output is a low logic level C - if there is an indeterminate output CLK D с D - if the output transitions from 0 to 1 E - if the output transitions from 1 to 0 1. What is the value of the output at point A? 2. What is the value of the output at point B? 3. What is the value of the output at point C? 4. What is the value of the output at point D? 5. What is the value of the output at point E? 6. What is the value of the output at point F? D E Farrow_forward2. Draw the timing diagram for the Clocked SR flip-flop at each of the instants t0 to t6 as described in the class meeting. a. at t0, Q is low, S is low, R is low b. at t0, Q is high, S is low, R is low Be sure to include the clock signal in the timing diagram.arrow_forwardDesign a sequential circuit with two JK flip-flops A and B, and one input Xin. When Xin = 0, the state of the circuit remains the same. When Xin = 1, the circuit goes through the state transitions from 00 to 01, to 11, to 10, back to 00, and repeats.arrow_forward
- Design a logic circuit with input signal A, control input B, and outputs X and Y to operate as follows: When B = 1, output X will follow input A, and output Y will be 0. When B = 0, output X will be 0, and output Y will follow input A.arrow_forwardDesigns a logic circuit that will allow a signal to pass to the output only when control inputs B and C are both HIGH; otherwise, the output will stay LOWarrow_forward6. Predict the output from each gate for the input variables shown: C A D B E Find out the values of C, D, E, F and G (show your calculation how you are getting the numbers) Input: A = 0 and B = 0 Find C, D. E, F, and G Each answer will be either 0 or 1arrow_forward
- 3. Study the ladder logic program in Figure 7-40 and answer the questions that follow: a. What type of timer has been programmed? b. What is the length of the time-delay period? c. What is the value of the accumulated time when power is first applied? d. When does the timer start timing? e. When does the timer stop timing and reset itself? f. When input LS1 is first closed, which rungs are true and which are false? L1 Input LS1 Ladder logic program Outputs L2 LS1 -TON TIMER ON DELAY Timer T4:0 -(EN)- Time base 1 Preset 10(DN) SOL A-fo Accumulated ° SOL B-of T4:0 SOL A 2 3 4 10 DN T4:0 SOL B DN T4:0 R EN T4:0 EN Figure 7-40 Ladder logic program for Problem 3. Rarrow_forwardDevelop the ladder logic diagram to fill the tank. 1. Filling the water tank up to 80%. When the tank is filled, turn ON the heater to raise the temperature up to 70-degree C.2. when this temperature is reached, turn OFF the heater & open the outlet valve.3. When the level in the tank falls below 10%, closes the output valve and start filling the tank again.4. A digital counter is used to monitor the number of times the tank is emptied (reaches 10%). Once the counter reaches to 8 times, the system is stopped.arrow_forward6. Write the minimized output Y for the logic circuit shown: C Y. Darrow_forward
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