Microelectronics: Circuit Analysis and Design
4th Edition
ISBN: 9780073380643
Author: Donald A. Neamen
Publisher: McGraw-Hill Companies, The
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Question
Chapter 17, Problem 17.6P
(a)
To determine
The value of the reference voltage
(b)
To determine
The value of logic 0 and logic 1 values at the output
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1.1
Given the timing diagram for 3-bit input A and two outputs, S and C in Figure la,
where A2 is the MSB and Ao is the LSB. Assume the output for the other input
conditions is don't cares (i.c. X). Determine the minimum logic circuit using NAND
logic configuration.
Az
Ac
S
C
Figure la
(a) Consider a combinational logic circuit in Figure Q.2 (a).i and Q.2 (a).ii. Determine the
Boolean equation for the output Y and then, replace the circuit with a single logic gate.
Figure Q.2 (a)i
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Voo
Figure Q.2 (a)ii
Below is an example of an NMOS logic circuit. For all of the MOSFETs in the circuit below,
assume V = 1 V and k = 50 mA/V².
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R₂ = 5600
R₁ = 4700
M3
Ao
M₁
M₂
a. Indicate and verify the state of each MOSFET and V for the following input
0
combinations. Fill-out the table below for each assumed state of the MOSFET for every
input combination. Use R approximation for linear operation and three significant
ds(on)
figures for the voltages.
Example:
M1 is assumed to be in saturation.
If Vgs = 2 V, Vds = 4V,
Vds > Vgs - Vth
4>2-1
4> 1 (ok)
Vgs > Vth (2>1)
A
B
M1 state
M2 state
M3 state
V
OV
OV
5 V
OV
b. What kind of logic circuit is implemented in the circuit above?
5V
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V₂
0
Chapter 17 Solutions
Microelectronics: Circuit Analysis and Design
Ch. 17 - Consider the differential amplifier circuit in...Ch. 17 - Prob. 17.2EPCh. 17 - The reference circuit in Figure 17.5 is to be...Ch. 17 - Assume the maximum currents in Q3 and Q4 of the...Ch. 17 - Prob. 17.5EPCh. 17 - Prob. 17.6EPCh. 17 - Prob. 17.1TYUCh. 17 - Prob. 17.2TYUCh. 17 - Prob. 17.7EPCh. 17 - Prob. 17.3TYU
Ch. 17 - The ECL circuit in Figure 17.19 is an example of...Ch. 17 - Consider the basic DTL circuit in Figure 17.20...Ch. 17 - The parameters of the TIL NAND circuit in Figure...Ch. 17 - Prob. 17.10EPCh. 17 - Prob. 17.5TYUCh. 17 - Prob. 17.6TYUCh. 17 - Prob. 17.7TYUCh. 17 - Prob. 17.8TYUCh. 17 - Prob. 17.11EPCh. 17 - Prob. 17.12EPCh. 17 - Prob. 17.9TYUCh. 17 - Prob. 17.10TYUCh. 17 - Prob. 17.11TYUCh. 17 - Prob. 1RQCh. 17 - Why must emitterfollower output stages be added to...Ch. 17 - Sketch a modified ECL circuit in which a Schottky...Ch. 17 - Explain the concept of series gating for ECL...Ch. 17 - Sketch a diodetransistor NAND circuit and explain...Ch. 17 - Explain the operation and purpose of the input...Ch. 17 - Sketch a basic TTL NAND circuit and explain its...Ch. 17 - Prob. 8RQCh. 17 - Prob. 9RQCh. 17 - Prob. 10RQCh. 17 - Explain the operation of a Schottky clamped...Ch. 17 - Prob. 12RQCh. 17 - Prob. 13RQCh. 17 - Sketch a basic BiCMOS inverter and explain its...Ch. 17 - For the differential amplifier circuit ¡n Figure...Ch. 17 - Prob. 17.2PCh. 17 - Prob. 17.3PCh. 17 - Prob. 17.4PCh. 17 - Prob. 17.5PCh. 17 - Prob. 17.6PCh. 17 - Prob. 17.7PCh. 17 - Prob. 17.8PCh. 17 - Prob. 17.9PCh. 17 - Prob. 17.10PCh. 17 - Prob. 17.11PCh. 17 - Prob. 17.12PCh. 17 - Prob. 17.13PCh. 17 - Prob. 17.14PCh. 17 - Prob. 17.15PCh. 17 - Prob. 17.16PCh. 17 - Prob. 17.17PCh. 17 - Prob. 17.18PCh. 17 - Consider the DTL circuit shown in Figure P17.19....Ch. 17 - Prob. 17.20PCh. 17 - Prob. 17.21PCh. 17 - Prob. 17.22PCh. 17 - Prob. 17.23PCh. 17 - Prob. 17.24PCh. 17 - Prob. 17.25PCh. 17 - Prob. 17.26PCh. 17 - Prob. 17.27PCh. 17 - Prob. 17.28PCh. 17 - Prob. 17.29PCh. 17 - Prob. 17.30PCh. 17 - Prob. 17.31PCh. 17 - Prob. 17.32PCh. 17 - Prob. 17.33PCh. 17 - For the transistors in the TTL circuit in Figure...Ch. 17 - Prob. 17.35PCh. 17 - Prob. 17.36PCh. 17 - Prob. 17.37PCh. 17 - Prob. 17.38PCh. 17 - Prob. 17.39PCh. 17 - Prob. 17.40PCh. 17 - Prob. 17.41PCh. 17 - Prob. 17.42PCh. 17 - Prob. 17.43PCh. 17 - Prob. 17.44PCh. 17 - Design a clocked D flipflop, using a modified ECL...Ch. 17 - Design a lowpower Schottky TTL exclusiveOR logic...Ch. 17 - Design a TTL RS flipflop.
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