The Kiwi™ memory architecture design team has a dilemma.  The team is considering several different memory configuration variations for an upcoming machine design.  Consider the following designs (All memory accesses are in terms of bytes, and all are using paging techniques):

Answer ii)

For a computer with 56-bit physical addresses and a 8-way set associative cache of 64 KB where each cache line has the capacity of holding 32 words. Assume the word size is 3 and the architecture is byte-addressable. Answer the questions below: a.How many bits are needed for tag, index, word offset, and byte offs. Show your derivations and assumptions. b.What are the start and end physical addresses, in hex as discussed in class, for cache line 300? Cache line count starts from 0. c.What is the total size, in KB, of this cache? d.What is the tag value, in hex, of address 0xABCDEF98765432?

Computer Architecture Consider the below one-bus organization find the micro-operations at each step for the following instructions: 1- Instruction Load (100), R4 (R4 M[M[100]]) 2- JUMP X, where X is a memory location that contains the address of the instruction to be executed

Consider a simple read-only memory (ROM) unit with 2-bit addressand 2-bit data buses.Draw the internal architecture of such a ROM unit includingtransistors, address and data signals, and the row decoder.? I have attached the answer to the question, but I am confused by it, if you could explain every step including how many transistors to use, where to place them and the basic procedure which could be used with other similar questions that would be helpful

Show how the decimal value 2019111310 would be stored by byte-addressable machines with 32-bit words, using little endian format and then big endian format. Assume the value starts at address 201916. Draw a diagram of memory and place the appropriate values in the correct (and labeled) memory locations.