How much of an improvement does segmented memory address translation have over straight translation?

How much more effective than direct translation is segmented memory address translation?

It is more probable that programs developed for zero-address, one-address, or two-address architecture will be lengthier (have more instructions). Why?

I'm confused about the distinction between a 7CH bit address and a 7CH byte address. When referring to a computer's memory map, what address does 7CH represent?

Convert the following Compact Memory Notation diagram into an Array Memory Notation diagram. Assume the addresses are 4-bit binary values and the data are 8-bit binary values. Hint: The solution to this question is simply the reformatted diagram in Array Notation.

The IBM System/370 architecture uses a two-level memory structure and refers to the two levels as segments and pages, although the segmentation approach lacks many of the features described earlier in this chapter. For the basic 370 architecture, the page size may be either 2 Kbytes or 4 Kbytes, and the segment size is fixed at either 64 Kbytes or 1 Mbyte. For the 370/XA and 370/ESA architectures, the page size is 4 Kbytes and the segment size is 1 Mbyte. Which advantages of segmentation does this scheme lack? What is the benefit of segmentation for the 370?

What advantages over direct translation can segmented memory address translation offer?

Programs written for zero-address, one-address, or two-address architecture are more likely to be longer (have more instructions). Why?

What advantages over direct translation can segmented memory address translation offer?

Given a computer with 300 memory locations, each 18-bit assessable, how many bits of addressing are needed?  Given a computer with 10-bit addressability and 5 bits for the address, what's the maximum number of memory this computer can have in bits?