A microprocessor has an increment memory direct instruction, which adds 1 to the value in a memory location. The instruction has five stages: fetch opcode(four bus clock cycles),fetch operand address (three cycles), fetch operand (three cycles) add 1 to operand (three cycles), and store operand (three cycles). a. By what amount (in percent) will the duration of the instruction increase if we have to insert two bus wait states in each memory read and memory write operation? b. repeat assuming that the increment operation takes 13 cycles instead of 3 cycles

A microprocessor has an increment memory direct instruction, which adds 1 to the value in a memory location. The instruction has five stages: fetch opcode(four bus clock cycles),fetch operand address (three cycles), fetch operand (three cycles) add 1 to operand (three cycles), and store operand (three cycles). a. By what amount (in percent) will the duration of the instruction increase if we have to insert two bus wait states in each memory read and memory write operation? b. repeat assuming that the increment operation takes 13 cycles instead of 3 cycles

Name: A microprocessor has an increment memory direct instruction, which add
Uploaded: 2024-03-20T06:51:23.000Z
Channel: Bartleby
Description: A microprocessor has an increment memory direct instruction, which adds 1 to the value in a memory location. The instruction has five stages: fetch opcode(four bus clock cycles),fetch operand address (three cycles), fetch operand (three cycles) add 1

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

See similar textbooks

Similar questions

If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the fetch cycle is 40% of the processor cycle time, what memory access speed is required to implement load operations with zero wait states and load operations with two wait states?
The time it takes to perform the fetch instruction and decode instruction steps is called the execution time. True or false?
A(n) ____________________ instruction copies data from one memory location to another.
Most Intel CPUs use the __________, in which each memory address is represented by two integers.
The contents of a memory location are copied to a register while performing a(n) __________________ operation.
A(n) __________ is a storage location implemented in the CPU.
When an instruction is first fetched from memory, its placed in the _________________ and then ________________to extract its components.
_____ is a CPU design technique in which instruction execution is divided into multiple stages and different instructions can execute in different stages simultaneously.
A computer has a 256K word addressable memory Module with 16 bits per word. The instruction set consists of 166 different instructions. All instructions have an operation code part (opcode) and an address part (allowing for only one address). Each instruction is stored in one word of memory. Based on the above, answer the following questions: a. How many bits are there in the main memory? (Represent it in power of 2) b. How many bits are needed for the opcode? c. How many bits are left for the address part of the instruction? d. How many additional instructions can be added to the existing 166 without affecting the assigned size of the opcode part? Justify.
Computer Science A computer uses a memory of 64K words with 16 bits in each word.It has the following registers: PC, AR, TR, AC, DR and IRA memory-reference instruction consists of two words: an 16-bit operation-code(one word) and an address field (in the next word).a-List the sequence of microoperations for fetching a memory reference instructionand then placing the operand in DR. Start from timing signal To.b-Design the logic control gates arrangement to perform the fetch instructions.
Suppose that the following instructions are found at the given locations in memory: 20 LDA 50 21 BRP 22 22 STO 51 50 100 51 100 Choose the contents of the registers: PC, MAR, MDR, IR, A at the end of fetch-execute cycle for instruction 22: PC MAR MDR IR A
A computer with a 32 bit word uses an instruction format that includes direct and indirect addressing of 8 megabytes and on of 16 registers. The highest order bits are used for the opcode, followed by the bits indicating the register, followed by indirect/direct bit, followed by the bits indicating memory address Draw the instruction word's format, showing how many bits are used for all four fields