Program Counter (PC), and ALU A B PC IR General MAR Purpose Registers ALU MDR Memory Bus

Computer Architecture (2) Consider the below one-bus organization find the micro-operations at each step for the following instructions:

The NOR instruction is not part of the RISC-V instruction set because the samefunctionality can be implemented using existing instructions. Write a short assembly codesnippet that has the following functionality: s3 = s4 NOR s5. Use as few instructions aspossible. Write RISC-V assembly code for placing the following immediate constants inregister s7. Use a minimum number of instructions.a) 59b) -199c) 0xDDCBE289d) 0x11236BDF

Consider a 16-bit processor in which the following appears in the main memory, starting at location 200.a. The first part of the first word (content at 200) indicates that this instruction loads a value into an accumulator; the value of 300 in location 201 may be part of the address calculator. The mode field specifies an addressing mode and, if appropriate, indicates a source register. a.  Assume that when used, the source register R1, which has a value of 500. b.  There is also a base register that contains the value 100, Assume that location 249 contains the value 399, location 250 contains the value 400, and so on.  Determine  the  effective  address  and  the  operand  to  be  loaded  for  the following  address modes:

The stack segment, data segment, and code segment are all separate entities. Next, ascertain which combination of registers is used to address data items inside each segment.

18 What is speculation as it relates to parallelization? It is the set of instructions that issues together in one clock cycle and the packet may be determined statically by the compiler or dynamically by the processor. It is a style of instruction set architecture that launches many operations that are defined to be independent in a single wide instruction, typically with many separate opcode fields. It is the number of clock cycles between a load instruction and an instruction that can use the result of the load without stalling the pipeline. O It is an approach whereby the compiler or processor guesses the outcome of an instruction to remove it as a dependence in executing other instructions.

microprocessor