Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN: 9780133594140
Author: James Kurose, Keith Ross
Publisher: PEARSON
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For a computer with 56-bit physical addresses and a 8-way set associative cache of 64 KB where each cache line has the capacity of holding 32 words. Assume the word size is 3
and the architecture is byte-addressable. Answer the questions below:
a.How many bits are needed for tag, index, word offset, and byte offs. Show your derivations and assumptions.
b.What are the start and end physical addresses, in hex as discussed in class, for cache line 300? Cache line count starts from 0.
c.What is the total size, in KB, of this cache?
d.What is the tag value, in hex, of address 0xABCDEF98765432?
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- Suppose a byte-addressable computer using set-associative cache has 216 bytes of main memory and a cache of 32 blocks, and each cache block contains 8 bytes.Q.) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache; that is, what are the sizes of the tag, set, and offset fields?arrow_forwardI have a little bit problem with my late quiz for computer architecture, I get the answer from my lecturer but I still don't feel fully understand, can I ask for some help: In a computer system, the memory has 32 blocks and the cache has 8 blocks. Assume there is only one word per block with 4 bytes in one word. The reference sequence in terms of word location is 0, 2, 4, 10, 5, 12, 8, 18, 13. If the cache is direct-mapped, how many misses do we have if the cache is initially empty? Can you give the hit or miss for each reference?arrow_forwardI'm confused about the distinction between a 7CH bit address and a 7CH byte address. When referring to a computer's memory map, what address does 7CH represent?arrow_forward
- In a certain computer, the virtual addresses are 32 bits long and the physical addresses are 48 bits long. The memory is word addressable. The page size is 16 kB and the word size is 2 bytes. The Translation Look-aside Buffer (TLB) in the address translation path has 64 valid entries. Hit ratio of TLB is 100% then maximum number of distinct virtual addresses that can be translated is K.arrow_forwardIf we had a computer that can only address data in bytes, but it has fully associative mapping, 16-bit main memory addresses, and 32-bit cache memory blocks. If each block is 16 bytes in size, then...(a) Count the number of bytes in the offset field.The tag field's size in pixels must be calculated (b).arrow_forwardSuppose we have a byte-addressable computer with a cache that holds 8 blocks of 4 bytes each. Assuming that each memory address has 8 bits, to which cache block would the hexadecimal address 0x2D map if the computer uses direct mapping? Blocks are numbered starting at 0arrow_forward
- What distinguishes a 7CH byte address from a 7CH bit address? Where does bit address 7CH sit in memory?arrow_forwardSuppose a computer using fully associative cache has 224 words of main memory and a cache of 512 blocks, where each cache block contains 16 words. How many blocks of main memory are there? What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag and offset fields? To which cache block will the memory reference 17042416 map?arrow_forwardSuppose a byte-addressable computer using 4-way setassociative cache has 216 words of main memory (where each word is 32 bits) and a cache of 32 blocks, where each block is four words. Show the main memory address format for this machine. (Hint: Because this architecture is byte addressable, and the number of addresses is critical in determining the address format, you must convert everything to bytes.)arrow_forward
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