memory range from 0xA000 to 0xCFFF (inclusive) Your design must be subject to the followi

On the Motorola 68020 microprocessor, a cache access takes two clock cycles. Data access from main memory over the bus to the processor takes three clock cycles in the case of no wait state insertion; the data are delivered to the processor in parallel with delivery to the cache. a. Calculate the effective length of a memory cycle given a hit ratio of 0.9 and a clocking rate of 16.67 MHz. b. Repeat the calculations assuming insertion of two wait states of one cycle each per memory cycle. What conclusion can you draw from the results?

A computer system contains a big endian byte addressable memory system with 8 separate memory modules. Each memory module is 32 bits wide and contains 134217728 cells. Cells within each memory module are numbered 0 through 134217727. a) If the memory employs high order interleaving, what is the 32-bit memory address of cell 1048578 within module 3? b) If the high order interleaved memory uses little-endian instead of big-endian storage order, what is the 32-bit memory address of cell 511 within module 1? c) If the memory employs low order interleaving, what is the 32-bit memory address of byte 1048575 within module 2? Bytes are numbered starting from 0. Express the address in hex. d) What is the main advantage of using low-order interleaved memory compared to using high-order interleaved memory?

A computer with a 32-bit 3.5 gigahertz scalar non- pipelined CPU needs to invert the colors of a 150 KB bitmap image file located in the RAM. To do this, each bit of the image must be complemented (Os are converted to 1s and vice-versa). Assume every instruction undergoes the following stages and each stage uses one CPU clock cycle: • Fetch • Decode • Read from memory • Execute • Write to memory Instructions: For this assignment, you must calculate how much time the computer will need to invert the image with a single-core and a dual core CPU. Show and explain your calculations and assumptions in a short paper and answer the following questions: • Will there be any parallel slowdown? Why or why not? Length: 2-3 page explanatory paper