For a direct mapped cache with 6-word a block, 33-bit address and 18-bits index , calculate the cache entry size in bits and must keep the calculations for submission later by showing it on your designed block diagram.

Consider a 32-bit computer using byte-addressable memory accessing different types of cache. Each cache consists of 256 blocks with one 32-bit word per block.  Specify how many bits are used for the tag, index or set, and byte offset for each type of cache listed in the table below.

For questions 1 through 3, use the following list of 32 bit memory address references, given as byte addresses. Note that you will need to convert them to binary: 3, 180, 43, 2, 191, 88, 190, 14, 180, 44, 186, 253

We are given a list of 64-bit memory address references, given as word addresses. Ox03, Oxb4, Ox2b, Ox02, Oxbf, Ox58, Oxbe, Ox0e, Oxb5, 0x2c, Oxba, Oxfd (A) For each of these references, identify the binary word address, the tag, and the index given a direct-mapped cache with 16 one- word blocks. Also list whether each reference is a hit or a miss, assuming the cache is initially empty. (B) For each of these references, identify the binary word address, the tag, the index, and the offset given a direct-mapped cache with two-word blocks and a total size of eight blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. (C) You are asked to optimize a cache design for the given references (i.e. addresses). There are three direct-mapped cache designs possible, all with a total of eight words of data: (i) Cache1 has 1-word blocks, (ii) Cache2 has 2-word blocks, and (iii) Cache3 has 4-word blocks.

1. Suppose we have a 64KB direct-mapped data cache with 32-byte blocks. a) Show how a 32-bit memory address is divided into tag, index and offset. Show clearly how many bits are in each field. b) How many total bits are there in this cache?

Please help with detailed explanation for problem C, don't copy solutions from other sources. Consider a byte addressing architecture with 64-bit memory addresses. a)Which bits of the address would be used in the tag, index and offset in a direct-mapped cache with 512 1-word blocks. b)Which bits of the address would be used in the tag, index and offset in a direct-mapped cache with 64 8-word blocks. c)What is the ratio of bits used for storing data to total bits stored in the cache in each of the above cases a and b?

Explain why it's difficult to design a universal cache replacement technique that works for all possible address sequences.

6. For a direct mapped cache comprising 16 single word blocks answer the following questions. Assume address and word sizes are both 32 bits and that the memory is byte addressed (4 bytes per 32-bit word). Enter answers as numbers only. How many index bits are there? How many offset bits are there? How many tag bits are there?

How many total bits are required for a direct-mapped cache with 64 KiB of data and 4-word blocks, assuming a 32-bit address? (Note: KiB means 21° Bytes, 1 word is 4 Bytes). Show your whi A work.

Explain the differences between a directly mapped cache and a fully associative cache.