Please help with detailed explanation for problem C, don't copy solutions from other sources. Consider a byte addressing architecture with 64-bit memory addresses. a)Which bits of the address would be used in the tag, index and offset in a direct-mapped cache with 512 1-word blocks. b)Which bits of the address would be used in the tag, index and offset in a direct-mapped cache with 64 8-word blocks. c)What is the ratio of bits used for storing data to total bits stored in the cache in each of the above cases a and b?

HELP WITH PART A,B, AND C

1. Write about the entire details of memory structure design and characteristics. 2. How much the number of bits calculation required for the logical address, if you considered the segment size is 1 k bytes and there are 32 segments? 3. In a paging model system, if a page size of 512 bytes and containing 64 entries of 11 bit each (including valid and invalid bit). How much the size of the physical address space needed?

help with part A B AND C.

A memory system has 4 KB byte-addressable main memory and a direct-mapped cache that consists of 8 blocks with 16 bytes per block. The following shows the main memory address format that allows us to map addresses from main memory to cache. Note: 12 bit address, 4 bit offset, 3 bit $block, and 5 bit tag Assume the cache directory shown below:

5. suppose a computer using fully associative cache has 224 bytes of byte-addressable main memory and a cache of 128 blocks, where each cache block contains 64 bytes. a) how many blocks of main memory are there? b) what is the format of a memory address as seen by the cache ; that is, what are the size of the tag and offset field. c) To which cache block will the memory address 0x01D872 map?

Computer science homework Please help me with this homework question.

Convert the following Compact Memory Notation diagram into an Array Memory Notation diagram. Assume the addresses are 4-bit binary values and the data are 8-bit binary values. Hint: The solution to this question is simply the reformatted diagram in Array Notation.

QUESTION 9 1. If a given memory address for a byte addressable machine is found in a cache that uses a 128 byte cache line size, the least significant 8 bits in the memory address will be used to select the byte(s) in the cache line to work with. True False QUESTION 10 1. SRAM memory is used predominately in: C SRAM memory is used predominately in: C motherboard main memory C BIOS PROM memory C SD card memory devices C CPU on-chip cache memory

The IBM System/370 architecture uses a two-level memory structure and refers to the two levels as segments and pages, although the segmentation approach lacks many of the features described earlier in this chapter. For the basic 370 architecture, the page size may be either 2 Kbytes or 4 Kbytes, and the segment size is fixed at either 64 Kbytes or 1 Mbyte. For the 370/XA and 370/ESA architectures, the page size is 4 Kbytes and the segment size is 1 Mbyte. Which advantages of segmentation does this scheme lack? What is the benefit of segmentation for the 370?