Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN: 9780133594140
Author: James Kurose, Keith Ross
Publisher: PEARSON
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- consider someone is using direct-mapped cache memory, each external memory address maps to what? a specific cache memory location one of many different cache memory locations a unique cache memory location, not shared with other external addresses a randomly-selected cache memory locationarrow_forwardWhat are the obstacles to developing a cache replacement mechanism that is compatible with any given address sequence?arrow_forwardDirect Mapping Example: CPU is searching an Instruction stored at RAM address 1110011010 in cache and doesn't find it. What happens then? Tag 0000000000 ?? 0000000001 ?? Block:0, (j=0) 0000000010 Instruction-1 Line1 = 1 Tag Tag 0000000011 Instruction-2 0000000100 Instruction-3 Instruction-4 Block:1, G=1) Solution: 0000000101 Line 2 (= 2) Tag 0000000110 Instruction-5 0000000111 Instruction-6 0000001100 Instruction-7 0000001101 Instruction-8 Block:2 0000001110 Data-1 (j=2) 0000001111 Data-2 Line.3 (3) 0000011100 Data-3 0000011101 Data-4 Tag 0000011110 Data-5 0000011111 Data-6 Cache Size = 64B Size of a line = 4B Total number of Lines in Cache: m 16 RAM Size = 1KB %3D 1111111100 %3D Size of a Block= 4B Total number of Blocks, M = 256 j = 0, 1, 2, ..255 (M-1) Block 255. G =255) 1111111101 1111111110 i = 0, 1, 2, ... 15 (m-1) 1111111111arrow_forward
- The phrases "unified cache" and "Hadley cache" should be defined.arrow_forwardIn a certain computer, the virtual addresses are 32 bits long and the physical addresses are 48 bits long. The memory is word addressable. The page size is 16 kB and the word size is 2 bytes. The Translation Look-aside Buffer (TLB) in the address translation path has 64 valid entries. Hit ratio of TLB is 100% then maximum number of distinct virtual addresses that can be translated is K.arrow_forwardConsider a 32-bit computer using byte-addressable memory accessing different types of cache. Each cache consists of 256 blocks with one 32-bit word per block. Specify how many bits are used for the tag, index or set, and byte offset for each type of cache listed in the table below.arrow_forward
- Question 4arrow_forwardFor a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. Tag 31-10 Index 9-5 a. What is the cache block size (in words)? b. How many entries does the cache have? Offset 4-0 c. What is the ratio between total bits required for such a cache implementation over the data storage bits?arrow_forwardIf a processor sends a cache-unfulfilled request while a block is being written back to main memory, should something happen?arrow_forward
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