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Q1. For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. Tag 31-10 Index 9-5 a) How many words of data in each cache line? b) How many lines does the cache have? c) What is the cache data size (in bits)? Offset 4-0 d) What is the ratio between total bits required for such a cache implementation over the data storage bits?

Q1. For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. Tag 31-10 Index 9-5 a) How many words of data in each cache line? b) How many lines does the cache have? c) What is the cache data size (in bits)? Offset 4-0 d) What is the ratio between total bits required for such a cache implementation over the data storage bits?

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Q1. For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. Tag 31-10 Index 9-5 a) How many words of data in each cache line? b) How many lines does the cache have? c) d) Offset 4-0 What is the cache data size (in bits)? What is the ratio between total bits required for such a cache implementation over the data storage bits?
Transcribed Image Text:Q1. For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. Tag 31-10 Index 9-5 a) How many words of data in each cache line? b) How many lines does the cache have? c) d) Offset 4-0 What is the cache data size (in bits)? What is the ratio between total bits required for such a cache implementation over the data storage bits?
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