Q1. For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. Tag 31-10 Index 9-5 a) How many words of data in each cache line? b) How many lines does the cache have? c) What is the cache data size (in bits)? Offset 4-0 d) What is the ratio between total bits required for such a cache implementation over the data storage bits?

Question 1             Consider a memory system that uses a 32-bit address at the byte level, plus a cache that uses a 64-byte line size. a)Assume a direct mapped cache with a tag field in the address of 20 bits. Show the address format and determine the following parameters: number of addressable units, number of blocks in main memory, number of lines in cache, size of tag b) Assume an associative cache. Show the address format and determine the following parameters: number of addressable units, number of blocks in main memory, number of lines in cache, size of tag. c) Assume a four-way set-associative cache with a tag field in the address of 9 bits. Show the address format and determine the following parameters: number of addressable units, number of blocks in main memory, number of lines in set, number of sets in cache, number of lines in cache, size of tag.

Q e

Please explain 1,2,and 3  Consider following cache elements Cache can hold 32 kB Data are transferred between main memory and the cache in blocks of 8 bytes each Main memory consists of 256 MB For the hexadecimal main memory address 1234567, show the following information (in hexadecimal format) Tag, Line, and Offset(word) values for Direct-mapped Cache   Tag and Offset(Word) values for Associative Cache  Tag, Set, and Offset(word) values for aa 4-way Set-associative Cache