Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN: 9780133594140
Author: James Kurose, Keith Ross
Publisher: PEARSON
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A cache designer wants to increase the size of a 4 KiB virtually indexed, physically tagged cache. Given the page size shown above, is it possible to make a 16 KiB direct-mapped cache, assuming 2 words per block? How would the designer increase the data size of the cache?
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- Given the following setup, how many words can be stored in the cache at the same time when the cache is full? A. Direct mapped cache Tag (T) Index (I) Word (W) Byte (B) 17 11 2 2 B. 2-way associative cache Tag (T) Index (I) Word (W) Byte (B) 18 10 2 2 C. 4-way associative cache Tag (T) Index (I) Word (W) Byte (B) 19 9 2 2 D. Fully associative cache Tag (T) Index (I) Word (W) Byte (B) 28 0 2 2arrow_forwardCaches are utilized to benefit from "spatial locality" and "temporal locality" in order to increase performance. What benefits do caches get from these two phenomena?arrow_forwardThe creator of a 4 KiB physically labeled and virtually indexed cache wants to increase its size. Is it possible to establish a 16 kilobyte direct-mapped cache with the above-mentioned page size and two words per block? How would the designer increase the cache's storage capacity?arrow_forward
- A cache designer wishes to enhance the size of a 4 KiB physically labeled, virtually indexed cache. Is it feasible to create a 16 KiB direct-mapped cache with the page size mentioned above, assuming two words per block? How would the designer expand the cache's data size?arrow_forwardA 4 KiB physically labelled, virtually indexed cache designer wants to expand it. Is a 16 KiB direct-mapped cache possible with the page size above and two words per block? How would the designer increase cache data?arrow_forward
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