Exercises 29 through 32 refer to a project consisting of 11 tasks (A through K) with the following processing times (in hours): A ( 10 ) , B ( 7 ) , C ( 11 ) , D ( 8 ) , E ( 9 ) , F ( 5 ) , G ( 3 ) , H ( 6 ) , I ( 4 ) , J ( 7 ) , K ( 5 ) . a. Explain why a schedule with N = 10 processors must have finishing time Fin ≥ 11 hours. b. Explain why it doesn’t make sense to put more than 10 processors on this project.
Exercises 29 through 32 refer to a project consisting of 11 tasks (A through K) with the following processing times (in hours): A ( 10 ) , B ( 7 ) , C ( 11 ) , D ( 8 ) , E ( 9 ) , F ( 5 ) , G ( 3 ) , H ( 6 ) , I ( 4 ) , J ( 7 ) , K ( 5 ) . a. Explain why a schedule with N = 10 processors must have finishing time Fin ≥ 11 hours. b. Explain why it doesn’t make sense to put more than 10 processors on this project.
Solution Summary: The author explains that a schedule with N=10 processors must have finishing time for the given tasks because the task C requires 11 hours to complete.
Exercises 29through 32 refer to a project consisting of 11 tasks (A through K) with the following processing times (in hours):
A
(
10
)
,
B
(
7
)
,
C
(
11
)
,
D
(
8
)
,
E
(
9
)
,
F
(
5
)
,
G
(
3
)
,
H
(
6
)
,
I
(
4
)
,
J
(
7
)
,
K
(
5
)
.
a. Explain why a schedule with
N
=
10
processors must have finishing time
Fin
≥
11
hours.
b. Explain why it doesn’t make sense to put more than 10 processors on this project.
An Jibble is produced on an assembly line consisting of six workstations. The total work content for one Jibble is 22 minutes based on the following standard times set forth for each station: 1 (4.0 minutes), 2 (6.5 minutes), 3 (4.0 minutes), 4 (2.5 minutes), 5 (2.0 minutes), 6 (3.0 minutes). If this assembly line runs 5 days per week, 8 hours per day and each station operator operates at 120% of standard, how many Jibbles can be produced in a week?
a.
Greater than or equal to 600 units.
b.
Greater than or equal to 500 units but less than 600 units.
c.
Less than 400 units.
d.
Greater than or equal to 400 units but less than 500 units.
the operation times for the major functional units in this implementation are the following:
Memory units: 200 picoseconds (ps)
ALU and adders: 50 ps
Register file (read or write): 25 ps
Assuming that the multiplexors, control unit, PC accesses, sign extension unit, and wires have no delay, which of the following implementations would be faster and by how much?
An implementation in which every instruction operates in 1 clock cycle of a fixed length.
An implementation where every instruction executes in 1 clock cycle using a variable length clock, which for each instruction is only as long as it needs to be. (Such an approach is not terribly practical, but it will allow us to see what is being sacrificed when all the instructions must execute in a single clock of the same length.)
To compare the performance, assume the following instruction mix: 20% loads, 15% stores, 40% ALU instructions, 20% branches, and 5% jumps.
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