Computer Organization and Design MIPS Edition, Fifth Edition: The Hardware/Software Interface (The Morgan Kaufmann Series in Computer Architecture and Design)
Expert Solution & Answer
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Chapter 5, Problem 5.7.6E

Explanation of Solution

Given:

Processor speed = 2GHz

Main memory access time = 100ns

First-level cache miss rate = 7%

Second-level cache = 12 cycles

Second-level cache miss rate = 3.5%

Second-level hit = 50 cycles

Base CPI = 1.5

Second-level 8-way set associative access = 28 cycles

Global miss rate with second-level 8-way set associative access = 1.5%

Second-level miss rate = 4% - 0.7%

Calculation:

Second-level direct-mapped on chip cache:

Memory miss cost = Processor speed + Main memory access                             = (× 109) × (100 × 109)                             = 200 cycles

Total CPI = (Base CPI) + (second level cache × first level miss rate) +                    (memory miss cost × Second-level cache miss rate)                = 1.5 + (12 × 7%) + (200 × 3.5%)                = 1.5 + (12 × 0.07) + (200 × 0.035)                = 1.5 + 0.84 + 7                = 9.34

External memory:

Total CPI            = (Base CPI) + (first-level miss per instruction × second-level hit)                                  × (main memory access cycles)     9.34                = 1.5 + (0.7% × 50) + (200)(4%  0.7n%)9.34  1.5          =  (0.07 × 50) + (200)(0.04  0.007n)     7.84               = 3.5 + 200(0.04  0.007n)7.84 3.5          = 200(0.04  0.007n)    4.34               = 200(0.04  0.007n)    4.34200             = 0.04  0.007n 

0.0217               = 0.04  0.007n0.0217  0.04  = 0.007n0.0183            = 0.007n            n           = 0.01830.007            n           = 2.61

Therefore, the second-level direct-mapped on chip cache is “2.61”.

Second-level 8-way set associative cache:

Memory miss cost = Processor speed + Main memory access                             = (× 109) × (100 × 109)                             = 200 cycles

Total CPI = (Base CPI) + (Second-level 8-way set associative access × first level miss rate) +                    (memory miss cost × Global miss rate with second-level 8-way set associative access)                = 1.5 + (28 × 7%) + (200 × 1.5%)                = 1.5 + (28 × 0.07) + (200 × 0.015)                = 1.5 + 1.96 + 3                = 6.46

External memory:

Total CPI            = (Base CPI) + (first-level miss per instruction × second-level hit)                                  × (main memory access cycles)     6.46                = 1.5 + (0.7% × 50) + (200)(4%  0.7n%)6.46  1.5          =  (0.07 × 50) + (200)(0.04  0.007n)     4.96                = 3.5 + 200(0.04  0.007n)4.96  3.5          = 200(0.04  0.007n)    1.46                 = 200(0.04  0.007n)  1.46200                 = 0.04  0.007n

0.0073               = 0.04  0.007n0.0073  0.04  = 0.007n0.0327            = 0.007n            n           = 0.03270.007            n           = 4.67

Therefore, the second-level 8-way set associative cache is “4.67”.

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Chapter 5 Solutions

Computer Organization and Design MIPS Edition, Fifth Edition: The Hardware/Software Interface (The Morgan Kaufmann Series in Computer Architecture and Design)

Ch. 5 - Prob. 5.2.5ECh. 5 - Prob. 5.2.6ECh. 5 - Prob. 5.3.1ECh. 5 - Prob. 5.3.2ECh. 5 - Prob. 5.3.3ECh. 5 - Prob. 5.3.4ECh. 5 - Prob. 5.3.5ECh. 5 - Prob. 5.3.6ECh. 5 - Prob. 5.4.1ECh. 5 - Prob. 5.4.2ECh. 5 - Prob. 5.4.3ECh. 5 - Prob. 5.4.5ECh. 5 - Prob. 5.4.6ECh. 5 - Prob. 5.5.1ECh. 5 - Prob. 5.5.2ECh. 5 - Prob. 5.5.3ECh. 5 - Prob. 5.5.4ECh. 5 - Prob. 5.5.5ECh. 5 - Prob. 5.5.6ECh. 5 - Prob. 5.6.1ECh. 5 - Prob. 5.6.2ECh. 5 - Prob. 5.6.3ECh. 5 - Prob. 5.6.4ECh. 5 - Prob. 5.6.5ECh. 5 - Prob. 5.6.6ECh. 5 - Prob. 5.7.1ECh. 5 - Prob. 5.7.2ECh. 5 - Prob. 5.7.3ECh. 5 - Prob. 5.7.4ECh. 5 - Prob. 5.7.5ECh. 5 - Prob. 5.7.6ECh. 5 - Prob. 5.8.1ECh. 5 - Prob. 5.8.2ECh. 5 - Prob. 5.8.3ECh. 5 - Prob. 5.8.4ECh. 5 - Prob. 5.9.1ECh. 5 - Prob. 5.9.2ECh. 5 - Prob. 5.9.3ECh. 5 - Prob. 5.10.1ECh. 5 - Prob. 5.10.2ECh. 5 - Prob. 5.10.3ECh. 5 - Prob. 5.10.4ECh. 5 - Prob. 5.10.5ECh. 5 - Prob. 5.10.6ECh. 5 - Prob. 5.11.1ECh. 5 - Prob. 5.11.2ECh. 5 - Prob. 5.11.3ECh. 5 - Prob. 5.11.4ECh. 5 - Prob. 5.11.5ECh. 5 - Prob. 5.11.6ECh. 5 - Prob. 5.12.1ECh. 5 - Prob. 5.12.2ECh. 5 - Prob. 5.12.3ECh. 5 - Prob. 5.12.4ECh. 5 - Prob. 5.12.5ECh. 5 - Prob. 5.12.6ECh. 5 - Prob. 5.13.1ECh. 5 - Prob. 5.13.2ECh. 5 - Prob. 5.13.3ECh. 5 - Prob. 5.13.4ECh. 5 - Prob. 5.13.5ECh. 5 - Prob. 5.13.6ECh. 5 - Prob. 5.14.1ECh. 5 - Prob. 5.14.2ECh. 5 - Prob. 5.14.3ECh. 5 - Prob. 5.14.4ECh. 5 - Prob. 5.14.5ECh. 5 - Prob. 5.14.6ECh. 5 - Prob. 5.15.1ECh. 5 - Prob. 5.15.2ECh. 5 - Prob. 5.15.3ECh. 5 - Prob. 5.15.4ECh. 5 - Prob. 5.16.1ECh. 5 - Prob. 5.16.2ECh. 5 - Prob. 5.17.1ECh. 5 - Prob. 5.17.2ECh. 5 - Prob. 5.17.3ECh. 5 - Prob. 5.17.4ECh. 5 - Prob. 5.17.5ECh. 5 - Prob. 5.17.6ECh. 5 - Prob. 5.18.1ECh. 5 - Prob. 5.18.2ECh. 5 - Prob. 5.18.3ECh. 5 - Prob. 5.18.4ECh. 5 - Prob. 5.18.5ECh. 5 - Prob. 5.18.6ECh. 5 - Prob. 5.19.1ECh. 5 - Prob. 5.19.2ECh. 5 - Prob. 5.19.3ECh. 5 - Prob. 5.19.4ECh. 5 - Prob. 5.19.6E
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