Chapter 5, Problem 5.4.1E

Explanation of Solution

Buffers needed for L1 and L2 caches:

• For L1 and L2 caches, single write buffer is needed. Reason is listed as follows:
• While the “miss” occurs, one can straightly update the part of the cache block into the buffer that will be waiting to write into L2, when the processor does not required stalling if the buffer is not occupied.
• For L2 and the memory, one can require two write and store buffers...