Computer Organization and Design MIPS Edition, Fifth Edition: The Hardware/Software Interface (The Morgan Kaufmann Series in Computer Architecture and Design)
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Chapter 5, Problem 5.7.4E

Explanation of Solution

Given:

Processor speed = 2GHz

Main memory access time = 100ns

First-level cache miss rate = 7%

Second-level cache = 12 cycles

Second-level cache miss rate = 3.5%

Third-level cache = 50 cycles

Base CPI = 1.5

Second-level 8-way set associative access = 28 cycles

Global miss rate with second-level 8-way set associative access = 1.5%

Calculation:

Memory miss cost = Processor speed + Main memory access                             = (× 109) × (100 × 109)                             = 200 cycles

Only a first-level cache in the system:

First-level cache CPI = 1.5 + (0.07 × 200)                                  = 1.5 + 14                                  = 15.5

Second-level direct-mapped cache:

L1 miss, L2 hit penalty = 12 cycles

Both miss penalty = 12 + 200                               = 212 cycles

Total CPI = (Base CPI) + (second level cache × first level miss rate) +                    (memory miss cost × Second-level cache miss rate)                = 1.5 + (12 × 7%) + (212 × 3.5%)                = 1.5 + (12 × 0.07) + (212 × 0.035)                = 1.5 + 0.84 + 7.42                = 9.76

Second-level 8-way set associative cache:

L1 miss, L2 hit penalty = 28 cycles

Both miss penalty = 28 + 200                               = 228 cycles

Total CPI = (Base CPI) + (second level cache × penalty) +                    (memory miss cost × second-level 8-way set associative access)                = 1.5 + (28 × 7%) + (228 × 1.5%)                = 1.5 + (28 × 0.07) + (228 × 0.015)                = 1.5 + 1.96 + 3.42                = 6.88

For double memory access time:

Memory miss cost = 2 × (Processor speed + Main memory access)                             = 2 × ((× 109) × (100 × 109))                             = 2 × 200                              = 400 cycles

Only a first-level cache in the system:

First-level cache CPI = 1.5 + (0.07 × 400)                                  = 1.5 + 28                                  = 29.5

Second-level direct-mapped cache:

L1 miss, L2 hit penalty = 12 cycles

Both miss penalty = 12 + 400                               = 412 cycles

Total CPI = (Base CPI) + (second level cache × first level miss rate) +                    (memory miss cost × Second-level cache miss rate)                = 1.5 + (12 × 7%) + (412 × 3.5%)                = 1.5 + (12 × 0.07) + (412 × 0.035)                = 1.5 + 0.84 + 14.42                = 16.76

Second-level 8-way set associative cache:

L1 miss, L2 hit penalty = 28 cycles

Both miss penalty = 28 + 400                               = 428 cycles

Total CPI = (Base CPI) + (second level cache × penalty) +                    (memory miss cost × second-level 8-way set associative access)                = 1.5 + (28 × 7%) + (428 × 1.5%)                = 1.5 + (28 × 0.07) + (428 × 0.015)                = 1.5 + 1.96 + 6.42                = 9.88

For half memory access time:

Memory miss cost = (Processor speed + Main memory access)2                             = ((× 109) × (100 × 109))2                             = 2002                              = 100 cycles

Only a first-level cache in the system:

First-level cache CPI = 1.5 + (0.07 × 100)                                  = 1.5 + 7                                  = 8.5

Second-level direct-mapped cache:

L1 miss, L2 hit penalty = 12 cycles

Both miss penalty = 12 + 100                               = 112 cycles

Total CPI = (Base CPI) + (second level cache × first level miss rate) +                    (memory miss cost × Second-level cache miss rate)                = 1.5 + (12 × 7%) + (112 × 3.5%)                = 1.5 + (12 × 0.07) + (112 × 0.035)                = 1.5 + 0.84 + 3.92                = 6.27

Second-level 8-way set associative cache:

L1 miss, L2 hit penalty = 28 cycles

Both miss penalty = 28 + 100                               = 128 cycles

Total CPI = (Base CPI) + (second level cache × penalty) +                    (memory miss cost × second-level 8-way set associative access)                = 1.5 + (28 × 7%) + (128 × 1.5%)                = 1.5 + (28 × 0.07) + (128 × 0.015)                = 1.5 + 1.96 + 1.92                = 5.38

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Chapter 5 Solutions

Computer Organization and Design MIPS Edition, Fifth Edition: The Hardware/Software Interface (The Morgan Kaufmann Series in Computer Architecture and Design)

Ch. 5 - Prob. 5.2.5ECh. 5 - Prob. 5.2.6ECh. 5 - Prob. 5.3.1ECh. 5 - Prob. 5.3.2ECh. 5 - Prob. 5.3.3ECh. 5 - Prob. 5.3.4ECh. 5 - Prob. 5.3.5ECh. 5 - Prob. 5.3.6ECh. 5 - Prob. 5.4.1ECh. 5 - Prob. 5.4.2ECh. 5 - Prob. 5.4.3ECh. 5 - Prob. 5.4.5ECh. 5 - Prob. 5.4.6ECh. 5 - Prob. 5.5.1ECh. 5 - Prob. 5.5.2ECh. 5 - Prob. 5.5.3ECh. 5 - Prob. 5.5.4ECh. 5 - Prob. 5.5.5ECh. 5 - Prob. 5.5.6ECh. 5 - Prob. 5.6.1ECh. 5 - Prob. 5.6.2ECh. 5 - Prob. 5.6.3ECh. 5 - Prob. 5.6.4ECh. 5 - Prob. 5.6.5ECh. 5 - Prob. 5.6.6ECh. 5 - Prob. 5.7.1ECh. 5 - Prob. 5.7.2ECh. 5 - Prob. 5.7.3ECh. 5 - Prob. 5.7.4ECh. 5 - Prob. 5.7.5ECh. 5 - Prob. 5.7.6ECh. 5 - Prob. 5.8.1ECh. 5 - Prob. 5.8.2ECh. 5 - Prob. 5.8.3ECh. 5 - Prob. 5.8.4ECh. 5 - Prob. 5.9.1ECh. 5 - Prob. 5.9.2ECh. 5 - Prob. 5.9.3ECh. 5 - Prob. 5.10.1ECh. 5 - Prob. 5.10.2ECh. 5 - Prob. 5.10.3ECh. 5 - Prob. 5.10.4ECh. 5 - Prob. 5.10.5ECh. 5 - Prob. 5.10.6ECh. 5 - Prob. 5.11.1ECh. 5 - Prob. 5.11.2ECh. 5 - Prob. 5.11.3ECh. 5 - Prob. 5.11.4ECh. 5 - Prob. 5.11.5ECh. 5 - Prob. 5.11.6ECh. 5 - Prob. 5.12.1ECh. 5 - Prob. 5.12.2ECh. 5 - Prob. 5.12.3ECh. 5 - Prob. 5.12.4ECh. 5 - Prob. 5.12.5ECh. 5 - Prob. 5.12.6ECh. 5 - Prob. 5.13.1ECh. 5 - Prob. 5.13.2ECh. 5 - Prob. 5.13.3ECh. 5 - Prob. 5.13.4ECh. 5 - Prob. 5.13.5ECh. 5 - Prob. 5.13.6ECh. 5 - Prob. 5.14.1ECh. 5 - Prob. 5.14.2ECh. 5 - Prob. 5.14.3ECh. 5 - Prob. 5.14.4ECh. 5 - Prob. 5.14.5ECh. 5 - Prob. 5.14.6ECh. 5 - Prob. 5.15.1ECh. 5 - Prob. 5.15.2ECh. 5 - Prob. 5.15.3ECh. 5 - Prob. 5.15.4ECh. 5 - Prob. 5.16.1ECh. 5 - Prob. 5.16.2ECh. 5 - Prob. 5.17.1ECh. 5 - Prob. 5.17.2ECh. 5 - Prob. 5.17.3ECh. 5 - Prob. 5.17.4ECh. 5 - Prob. 5.17.5ECh. 5 - Prob. 5.17.6ECh. 5 - Prob. 5.18.1ECh. 5 - Prob. 5.18.2ECh. 5 - Prob. 5.18.3ECh. 5 - Prob. 5.18.4ECh. 5 - Prob. 5.18.5ECh. 5 - Prob. 5.18.6ECh. 5 - Prob. 5.19.1ECh. 5 - Prob. 5.19.2ECh. 5 - Prob. 5.19.3ECh. 5 - Prob. 5.19.4ECh. 5 - Prob. 5.19.6E
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