Programmable Logic Controllers
5th Edition
ISBN: 9780073373843
Author: Frank D. Petruzella
Publisher: McGraw-Hill Education
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Chapter 15.3, Problem 2P
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- If the solenoid gate fails to energize as programmed then, the problem occurs with the wiring to the solenoid.
- From the given diagram, when the bit value of “T_SOL_Delay.DN” is set, the output status of solenoid must be in “ON” condition...
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PROBLEM NO.1 (odd numbers)
Design a Gray code converter to drive a seven-segment indicator. The four inputs to the converter circuit (A, B, C,
and D in Figure 1) represent a decimal digit coded using the Gray code. Assume that only input combinations
representing the digits 0 through 9 can occur as inputs, so that the six unused combinations are don't-care terms.
Design your circuit using only two-, three-, and four-input NAND gates and inverters. Try to minimize the numbers
of gates and inverters required. The variables A, B, C, and D will be available from toggle switches.
6 (not) for 6. Use 9 (not 9 ) for 9.
Figure 1
Any solution with 20 or fewer gates and inverters (not counting the four inverters for the inputs) is
1. Design a simple logic circuit for a Set/Reset (SR) Latch, based on any actual application of latches.
2.) Describe your design using at least three (4) sentences.
Note: Look at the example guide on the image.
IV. PROCEDURES:
For the AND gate look on the data sheets, connect the circuit on Breadboard and test the gate.
Using logic switches SW1 and SW2, apply the logic levels 0 and 1 to gate inputs
Create a truth table and record the results
Also simulate the given gate using the Circuit Wizard simulation software
Obtain the corresponding circuit diagram using the simulation software of the Boolean expression
F((A,B,C)=
АВ* AC * ВС
From the obtain circuit diagram develop the corresponding truth table
From the figure below obtain the equivalent Boolean expression and develop its corresponding truth Table
АП
сПо-
Boolean Expression:
Z= (AB)(CD)
Chapter 15 Solutions
Programmable Logic Controllers
Ch. 15.1 - Prob. 1RQCh. 15.1 - Prob. 2RQCh. 15.1 - Prob. 3RQCh. 15.1 - Prob. 4RQCh. 15.1 - Prob. 5RQCh. 15.1 - Prob. 6RQCh. 15.1 - Prob. 7RQCh. 15.1 - Prob. 8RQCh. 15.1 - Prob. 9RQCh. 15.1 - Prob. 10RQ
Ch. 15.1 - Prob. 11RQCh. 15.1 - Compare the accessibility of program scope and...Ch. 15.1 - Prob. 13RQCh. 15.1 - What is the difference between a produced tag and...Ch. 15.1 - Prob. 15RQCh. 15.1 - State the data type used for each of the...Ch. 15.1 - Describe the make-up of a predefined structure.Ch. 15.1 - Describe the make-up of a module-defined...Ch. 15.1 - Describe the make-up of a user-defined structure.Ch. 15.1 - Prob. 20RQCh. 15.1 - Prob. 21RQCh. 15.1 - Prob. 22RQCh. 15.1 - Prob. 23RQCh. 15.2 - Prob. 1RQCh. 15.2 - Prob. 2RQCh. 15.2 - Prob. 3RQCh. 15.2 - Prob. 4RQCh. 15.2 - Prob. 5RQCh. 15.2 - Prob. 6RQCh. 15.2 - Prob. 7RQCh. 15.2 - Prob. 8RQCh. 15.2 - Prob. 9RQCh. 15.2 - Prob. 10RQCh. 15.2 - Prob. 11RQCh. 15.2 - Extend control of the original ControlLogix...Ch. 15.2 - Prob. 3PCh. 15.3 - Prob. 1RQCh. 15.3 - Prob. 2RQCh. 15.3 - Prob. 3RQCh. 15.3 - Prob. 4RQCh. 15.3 - Prob. 5RQCh. 15.3 - Prob. 6RQCh. 15.3 - Prob. 7RQCh. 15.3 - Prob. 8RQCh. 15.3 - Prob. 9RQCh. 15.3 - Prob. 10RQCh. 15.3 - Prob. 11RQCh. 15.3 - Prob. 12RQCh. 15.3 - Modify the original CLX ten-second TON timer...Ch. 15.3 - Prob. 2PCh. 15.3 - Prob. 3PCh. 15.3 - Prob. 4PCh. 15.3 - Prob. 5PCh. 15.3 - Prob. 6PCh. 15.4 - Prob. 1RQCh. 15.4 - Prob. 2RQCh. 15.4 - Prob. 3RQCh. 15.4 - Prob. 4RQCh. 15.4 - Prob. 5RQCh. 15.4 - Prob. 6RQCh. 15.4 - Prob. 7RQCh. 15.4 - Prob. 1PCh. 15.4 - Prob. 2PCh. 15.5 - Prob. 1RQCh. 15.5 - Prob. 2RQCh. 15.5 - Prob. 3RQCh. 15.5 - Prob. 4RQCh. 15.5 - Prob. 5RQCh. 15.5 - Construct a ControlLogix ladder rung with compare...Ch. 15.5 - Prob. 2PCh. 15.5 - A single pole switch is used in place of the two...Ch. 15.6 - Prob. 1RQCh. 15.6 - Name the four basic elements of an FBD.Ch. 15.6 - Prob. 3RQCh. 15.6 - Prob. 4RQCh. 15.6 - Prob. 5RQCh. 15.6 - Prob. 6RQCh. 15.6 - Prob. 7RQCh. 15.6 - Prob. 8RQCh. 15.6 - Prob. 9RQCh. 15.6 - Prob. 10RQCh. 15.6 - Prob. 11RQCh. 15.6 - How is a function block feedback loop created?Ch. 15.6 - Prob. 13RQCh. 15.6 - Prob. 14RQCh. 15.6 - Prob. 1PCh. 15.6 - Prob. 2PCh. 15.6 - Prob. 3PCh. 15.6 - Prob. 4PCh. 15.6 - Prob. 5P
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- (a) Write the logic expression for the output 'Y' of the circuit given below. (b) Write the Truth table and pin diagram for EXOR gate.arrow_forwardA pulse is applied to each input of an exclusive-OR gate. One pulse goes HIGH at t = 0 and goes back LOW at t = 1 ms. The other pulse goes HIGH at t = 0.8 ms and goes back LOW at t = 3 ms. The output pulse can be described as follows:(a) It goes HIGH at t = 0 and back LOW at t = 3 ms.(b) It goes HIGH at t = 0 and back LOW at t = 0.8 ms.(c) It goes HIGH at t = 1 ms and back LOW at t = 3 ms.(d) both answers (b) and (c)arrow_forwardI need a gate level design from this boolean expression. This should be Nand gates and all variable should be inputs; A, B , C, D, E, F. Thank you.arrow_forward
- Answer the following questions: If a 3-input XOR gate has eight input possibilities, how many of those possibilities will result in a HIGH output? What type of logic circuit is represented by the figure 4 shown below? Name the gate whose output is HIGH if and only if all the inputs are LOW If a JK latch has J=1, K=0 initially. When the K input goes high, what will be the output?arrow_forwardA pulse is applied to each input of a 2-input NOR gate. One pulse goes HIGH at t = 0 and goes back LOW at t = 1 ms. The other pulse goes HIGH at t = 0.8 ms and goes back LOW at t = 3 ms. The output pulse can be described as follows:(a) It goes LOW at t = 0 and back HIGH at t = 3 ms.(b) It goes LOW at t = 0.8 ms and back HIGH at t = 3 ms.(c) It goes LOW at t = 0.8 ms and back HIGH at t = 1 ms.(d) It goes HIGH at t = 0.8 ms and back LOW at t = 1 ms.arrow_forwardConvert the following logic gate circuit into a Boolean expression. Write Boolean subexpression next to each gate. t1 y t2 |t4 t3arrow_forward
- What Hamiltonian must be applied to create a Hadamard gate? How long should that Hamiltonian be applied to create a Hadamard gate in terms of the variables of the Hamiltonian and it?arrow_forwardComplete the timing diagram for the following circuit. Assume that the signal delay through the NOR gates is 3 ns, and the delay through the NOT gate is 1 ns.arrow_forwardSuppose, the password for a security lock system is 5-digit in length and consists of binary digits only. Design an optimized circuit using basic logic gates only for the system which opens the lock when there are even number of 1’s in the password. Show your work in detail and draw circuit diagram neatly for the lock system.arrow_forward
- "Design a combinational circuit defined by the Boolean function F(X,Y,Z) = (X'+Y)(X'+Z')(X'+Y'+Z), using a decoder and external gate/s. In order to implement this, the size of the decoder should be and we need to include and external gate."arrow_forwarda) Write the Boolean expression for output x in the circuit. b) Create a complete analysis table for the circuit by finding the logic levels present at each gate output for each of the 16 possible input combinations. Hint: You can use nodes/intermediate columns in truth table after each logical gate operation to facilitate the work. Which is the answer? I need all the steps to understand, thanks.arrow_forwardMethodology- I am using Verilog and the Vivado Software to design and deploy a logic system on an FPGA. This system should have the capability to control the Pmod seven-segment display, causing it to cycle through the numbers 0, 1, 2, ..., 8, 9 in a continuous loop. Can you detail the steps taken to design the digital logic circuits using Verilog including any diagrams, schematics, or code snippits to illustrate the design?arrow_forward
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