Write operations occur in the first half of the clock cycle and reads occur in the second half of the clock cycle. The table below shows the pipelining diagram for three instructions. Inst/CC 1 2 3 4 5 6 Inst. 1 IF ID EXE MEM WB Stall Inst. 2 Inst. 3 7 8 IF ID EXE MEM WB IF ID EXE MEM WB Where CC stands for clock cycle, stalls are shown as empty rows, and forwarding is indicated between associated stages using an arrow. LDUR X0, [X0, #5] SUB X2, X0, XO SUB X3, X1, X2 ADD X3, X2, X3 ADD X4, X1, X3 a. First assume forwarding is not available, show a similar table for the following sequence of instructions and indicate stalls with empty rows. How many cycles are needed to execute the above sequence of instructions?

A(n) ________________ instruction always alters the instruction execution sequence. A(n) ______________ instruction alters the instruction execution sequence only if a specified Condition is true.

(Practice) Show how the name KINGSLEY is stored in a computer that uses the ASCII code by drawing a diagram similar to Figure 2.7, shown previously.

(Heat transfer) The formula developed in Exercise 5 can be used to determine the cooling time, t, caused only by radiation, of each planet in the solar system. For convenience, this formula is repeated here (see Exercise 5 for a definition of each symbol): t=Nk2eAT3fin A=surfaceareaofasphere=4r2 N=numberofatoms=volumeofthespherevolumeofanatom Volume of a sphere sphere=43radius3 The volume of a single atom is approximately 11029m3 . Using this information and the current temperatures and radii listed in the following chart, determine the time it took each planet to cool to its current temperature, caused only by radiation.

Describe the operation of a MOVE instruction. Why is the name MOVE a misnomer?

In the ________, memory addresses consist of a single integer.

If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the fetch cycle is 40% of the processor cycle time, what memory access speed is required to implement load operations with zero wait states and load operations with two wait states?

_____ is a CPU design technique in which instruction execution is divided into multiple stages and different instructions can execute in different stages simultaneously.

Most Intel CPUs use the __________, in which each memory address is represented by two integers.

In a CPU, _______ arithmetic generally is easier to implement than _______ arithmetic because of a simpler data coding scheme and data manipulation circuitry.