True/False Run times of the typical five stages to execute an instruction are as given in some units of time:  Instruction Fetch: 10 Instruction Decode: 15 Execute: 30 Memory: 50 Write Back: 20 If this is implemented as a pipelined versus a non-pipelined machine, then depending on the absence of hazards, one could expect the speedup to be about 2.5.

two different processors execute same instructions, Processor one has 4Ghz clock rate and 1.5 CPI, processor two has 1.3GHz and 2.2 CPI. 1)find the processor with the highest performance expressed in instructions per second 2)if both processors execute a program in 15seconds, what is the number of cycles and instructions

Assume a 5-stage pipelined CPU (IF – ID – MU- EX – WR) requires following time for different sections: Required time 15 ns Pipeline stages Fetch Unit Decode Unit 10 ns 20 ns Memory Unit Execution Unit 8 ns 15 ns Write back Unit The maximum delay required to transfer contents from one state to another is 2ns. a) Show the time steps of pipelining stages for the first 10 instructions of a program. Assume that Instruction-4 is a conditional loop instruction. If the condition is TRUE, CPU runs instructions: 7 - 9 twice. Please note that a single-port RAM is used with the system, such that CPU read only one data from RAM or save only one data to RAM at a time. Calculate the execution time for the first 10 instructions of a program as well. b) Show the time steps and calculate the execution time for above problem while a multiport RAM is used with the system.

Make sure to find the following: Total (actual) time: Time wasted: % Wasted:

During the processing of which of the following instructions is the use of an adder not required? (Processing of an instruction spans the whole instruction cycle.) Neglect the requirement of incrementing PC in the FETCH phase of the instruction cycle, which can be accomplished with a simpler increment circuit and does not require a full blown adder. O JMP AND ADD OST O LDR