clock cycle at which the first of the instructions is fetched as clock cycle 1. Assume that if one instruction reads a register during the same clock cycle as another instruction is writing it, the new value will be read. Do not reorder the instructions. Instructions are fetched and executed exactly in the order given below, with the pipeline stalling if necessary. addi $s2, $s2, 1 li $s6, 5 add $s1, $s2, $s3 move $s5, $s6 lw $t1, 0($s5)

E In the following code block(Reference:Q11), you will a set of assembly instructions with corresponding line numbers (line numbers are for informational purpose only and they are not part of the source code). 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 mov edx, 5 dec ecx jmp LABEL1 mov eax, 1 LABEL1: mul edx jmp ecx mov edx, 0678h sub edx, eax jmp DWORD PTR [edx] neg ebx add ecx, ebx mov eax, 0 For each of the conditions/scenario listed below, indicate the corresponding line number (that cause or is associated with the condition/scenario). Enter 0 (Zero) if the condition is not caused by the block of code. 1) Memory indirect jump: type your answer... type your answer... type your answer... type your answer... 2) Register indirect jump: 3) Relative short jump: type your answer... 5) Two's complement type your answer... 4) Relative near jump: 6) Unreachable code