Question 1: A computer system has a CPU that has a 16-bit address bus and 8-bit data bus. The CPU has to be connected to the following memories: A 16K x 8 EEPROM at starting address 0000H A 4K x 8 RAM at starting address 8000H Design an address decoding circuitry to meet the above specifications, and show how those two memory chips will be interfaced with the CPU.

A large endian byte addressed memory system with eight distinct memory modules is included in a computer system. Each memory module has 134217728 cells and is 32 bits wide. a) What is the 32-bit memory address of cell 1048578 in module 3 if the memory uses high order interleaving? b) What is the 32-bit memory address of byte 1048575 inside module 2 if the memory uses high order interleaving? c) What is the 32-bit memory address of cell 511 inside module 1 if the high order interleaved memory utilises little endian storage order instead of big endian storage order?

Computer Architecture Consider the below one-bus organization find the micro-operations at each step for the following instructions: 1- Instruction Load (100), R4 (R4 M[M[100]]) 2- JUMP X, where X is a memory location that contains the address of the instruction to be executed