We want to build a byte organized main memory of 8 GB for a 32-bit CPU architecture composed of byte organized memory modules of 30-bit address and 8-bit data buses each. a) Draw the interface of the main memory by clearly indicating the widths of the buses. b) How many memory modules would be necessary to build the memory system? c) Design the main memory internal organization built out of the above memory modules (use multiplexers and/or decoders as needed) by clearly indicating the widths of the used busses

A computer employs RAM chips of 512 x 16 and ROM chips of 1024 x 8. The computer system needs 4K bytes of RAM and 2K bytes of ROM along with interface unit of 128 registers each. A memory mapped I/0 configuration is used. The two higher order bits are assigned for RAM, ROM and interface as 00, 01 and 10 respectively. a) How many RAM and ROM chips are needed

Part 1: Registers of Different Sizes Registers are fast, but small memory locations that are inside of a CPU. They are used for the CPU's internal computations. A modern 32-bit CPU only contains 8 registers that we are capable of manipulating: EAX, EBX, ECX, EDX, EBP, ESP, ESI, and EDI. Each of these is a 32-bit register (meaning they each hold 32 digit binary numbers). There are many situations where we would want to use smaller portions of data than 32 bits. For example, when working with characters we are primarily using byte data, since each character is stored in just a single byte (which you should know is 8 bits). For this purpose, portions of the 32-bit registers can be referenced directly as if they were smaller registers. The register EAX holds 32-bits. The register AX is the bottom half of EAX, holding just 16 bits. The register AL is the bottom half of AX, holding just 8 bits. There is also AH, which is the top half of AX and also holds 8 bits. EBX, ECX, and EDX can also be…

Consider a 32-bit microprocessor, with a 16-bit external data bus, driven by an 8-MHz input clock. Assume that this microprocessor has a bus cycle whose minimum duration equals four input clock cycles. What is the maximum data transfer rate across the bus that this microprocessor can sustain in bytes/s? To increase its performance, would it be better to make its external data bus 32 bits or to double the external clock fre- quency supplied to the microprocessor? State any other assumptions you make and explain. Hint: Determine the number of bytes that can be transferred per bus cycle.

The IBM System/370 architecture uses a two-level memory structure and refers to the two levels as segments and pages, although the segmentation approach lacks many of the features described earlier in this chapter. For the basic 370 architecture, the page size may be either 2 Kbytes or 4 Kbytes, and the segment size is fixed at either 64 Kbytes or 1 Mbyte. For the 370/XA and 370/ESA architectures, the page size is 4 Kbytes and the segment size is 1 Mbyte. Which advantages of segmentation does this scheme lack? What is the benefit of segmentation for the 370?

Computer Architecture Consider the below one-bus organization find the micro-operations at each step for the following instructions: 1- Instruction Load (100), R4 (R4 M[M[100]]) 2- JUMP X, where X is a memory location that contains the address of the instruction to be executed

Consider a simple read-only memory (ROM) unit with 2-bit addressand 2-bit data buses.Draw the internal architecture of such a ROM unit includingtransistors, address and data signals, and the row decoder.? I have attached the answer to the question, but I am confused by it, if you could explain every step including how many transistors to use, where to place them and the basic procedure which could be used with other similar questions that would be helpful

Part 1: Registers of Different Sizes Registers are fast, but small memory locations that are inside of a CPU. They are used for the CPU's internal computations. A modern 32-bit CPU only contains 8 registers that we are capable of manipulating: EAX, EBX, ECX, EDX, EBP, ESP, ESI, and EDI. Each of these is a 32-bit register (meaning they each hold 32 digit binary numbers). There are many situations where we would want to use smaller portions of data than 32 bits. For example, when working with characters we are primarily using byte data, since each character is stored in just a single byte (which you should know is 8 bits). For this purpose, portions of the 32-bit registers can be referenced directly as if they were smaller registers. The register EAX holds 32-bits. The register AX is the bottom half of EAX, holding just 16 bits. The register AL is the bottom half of AX, holding just 8 bits. There is also AH, which is the top half of AX and also holds 8 bits. EBX, ECX, and EDX can also be…

We want to build a word organized main memory of 8 GB for a 32-bit CPU architecture composed of word organized memory modules of 30-bit address and 8-bit data buses each. a) Draw the interface of the main memory by clearly indicating the widths of the buses. b) Howmanymemorymoduleswouldbenecessarytobuildthememorysystem? c) Design the main memory internal organization built out of the above memory modules (use multiplexers and/or decoders as needed) by clearly indicating the widths of the used busses d) CanweusethismemorysystemasRAMfortheCPUinProblem1?Explainyouranswer.