Problem 4: Voting 2 out of 4 logic is a redundancy scheme utilized in control systems to enhance reliability. It operates by evaluating four input signals and generating a single output based on the majority vote of those inputs. Specifically, the output signal becomes active only when at least two of the input signals are active. Inputs: The voting logic requires four input signals (A, B, C, and D), each originating from distinct sources or sensors. ☐ Output: A solitary output signal (designated as Y) is produced based on the majority vote result of the inputs. Logic Gates: The inputs are connected to a series of AND and OR gates that implement the 2 out of 4 voting logic. Voting: The logic gates are arranged in such a way that the system requires at least two inputs to be in the same state (either high or low) to consider the input valid.

Task 1: You are to design a 4-bit arithmetic unit that consists of a 4-bit adder/subtractor circuit. The arithmetic unit takes as inputs two 4-bit numbers (A and B) and one control input (M) add/subtract selector that selects the type of operation the unit will perform. When the input control is ‘0’, the input numbers are added. When it is set to ‘1’, the two input numbers are subtracted (A - B)

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Choose the true H-bridge motor statements in the list below. O The L298N has a PWM input signal that can be used to control the motor direction. (false, it controls the speed of the motor. O You should always transition through the "Off" state when changing direction with the H-bridge. O The H-bridge provides a means of controlling a motors spin direction. O If all four H-bridge switches are open, the motors will spin. O The H-bridge uses four switches to control the current flow.

Procedure: You are to design a 4-bit arithmetic unit that consists of a 4-bit adder/subtractor circuit. The arithmetic unit takes as inputs two 4-bit numbers (A and B) and one control input (M) add/subtract selector that selects the type of operation the unit will perform. When the input control is ‘0’, the input numbers are added. When it is set to ‘1’, the two input numbers are subtracted (A - B). Question: Two 4-bit Adder/Subtractor Circuit: Design and construct a 4-bit adder/subtractor circuit. Draw the produced circuit.

What is the result of the following FAL instruction? Input L1 Loo a. O b. O C. A HE e. Ladder logic program FAL FILE ARITH/LOGICAL Control Length Position Mode Destination Expression None of the choices (EN) (DN) Incremental (ER) #N7:101 R6:2 6 0 0 N7:100 On successive transitions, data will be copied from N7:100 into the next position in the file #N7:101 until N7:106 is reached Once input A becomes true, data will be copied #N7:101 into the next address of N7:100 O d. On successive transitions, data will be copied #N7:101 into the next address of N7:100 Once input A becomes true, data will be copied six times from #N7:100 into the word #N7:101

The logic function implemented by the multiplexer circuit is (ground implies a logic "0") 4x1 MUX 1。 1₁ 1₂ 13 S₁ S₂ P Q Y -F

(a) Construct a transition table and state graph for the circuit shown in Figure 5. Is the circuit a Mealy or Moore circuit? Does the circuit have any unused states? (b) Assume 00 is the initial state. Draw a timing diagram for the input sequence X = 00110. (c) What is the output sequence for the input sequence? X J1 Q1 CLK K1 J2 Q2 K2 Q2 Figure 5

A multiplexer has 3 select lines and two enables. How many other inputs are there? How many TOTAL inputs are there? How many output/outputs are there? Draw a block diagram of this multiplexer.

Here is the data flow diagram for a particular instruction. The various values shown indicate the state of the machine after the action of this instruction. The question mark locates this instruction in memory. GatePC DR 100 GateMARMUX RO X2FFF PC X RI x3006 MARMUX TRAPVECTOR R2 x3005 X0:0 PCMUX R3 x3004 ZEXT R4 x3003 OFPSETŐ OR R5 x3002 PC OR BASER R6 x3001 PCOFFSET (7:0) R7 x3000 ADDR2MUX ADDRIMUX SR2 SRI (100 SEXT IMMS SEXT SRZMUX SEXT FINITE [50] SEXT STATE [40] MACHINE Arith/Logic Operation AL select IRO01 A/L RESULT LOGIC GateALU Gate MDR 16 16 MDR MAR T16 МЕМORY x 30 0O x 30 0 1 X 3:0:0 2 x3003 x3004 x 30 03 x3001 x: 3:0 0 4 X 30 05 X300 6 x3000 x3006 x3002 What is that instruction in binary? (You may use any number of spaces to organize the bits.) address instruction х3002