Let's pretend for a moment that we have a byte-addressable computer with fully associative mapping, 16-bit main memory addresses, and 32 blocks of cache memory. The following holds true if each block is 16 bits in size: a) Determine how many bytes the offset field is. Measure the tag field's width and height in pixels (b).

4. The figure below shows an 8-way interleaved, byte-addressable memory. The total size of the memory is 4 KB. The elements A[i]G) of a 2-dimensional array A are 4-bytes (one-word) in length and can be stored in the memory as shown, where 0 < ij <7. The width of the bus between CPU and memory is 32 bits, that is, it can carry only one word at a time. Bank 1 Bank 7 Bank 0 31 7 A[7][0] A[I][0] A[0]|0] 32 A[7]1] 64 A[7]|2] A[I][2] A[0||2] RANKO 255 224 AI기기 A[I][7] A[0||7) RANKN ...... Since the address space of the memory is 4 KB, 12 bits are needed to uniquely identify each memory location, i.e., Addr[11:0]. Find out and explain which bits of the address will be used for: • Byte on bus: Addr […... :...] Bank index bits within a bank: Addr [.... .] • Chip select address bits within a rank: Addr […... .] • Rank bits: Addr […... :....]

Suppose a computer system uses 16-bit addresses for both its virtual and physical addresses. In addition, assume each page (and frame) has size 256 bytes. How many bits are used for the page number? How many bits are used for the offset? 8 bits each. With this system, what’s the maximum number of pages that a process can have? 256 Suppose that each entry in the page table comprises 4 bytes (including the frame number, the valid bit, and miscellaneous “bookkeeping bits”). An OS uses an array to store the page table. What is the size of the page table? 1024 Bytes Furthermore, suppose the first 6 pages of a process map to frames 222 to 227 (as decimal numbers), and the last 5 pages of the process map to frames 1 to 5 (also decimal numbers). All other pages are invalid. Draw the page table, including the valid bit and the frame number. DONE Translate the following virtual addresses to physical addresses, and show how you obtain the answers. (Hint: You do not need to convert…

There are many parameters that could be used to describe disk performance; among them are:   number of bits per track disk capacity (in bits) number of disk surfaces rotational speed rotational latency transfer rate tracks per surface sectors per track blocks per track sectors per block seek time speed of disk arm block-read time number of blocks   Some of these parameters are independent, and others are (approximately) linearly related. That is, doubling one doubles the other. Decide which of these parameters are linearly related. Then, select from the list below, the relationship that is true, to within a close approximation. Note: none of the statements may be true exactly, but one will always be much closer to the truth than the other three. Also note: you should assume all dimensions and parameters of the disk are unchanged except for the ones mentioned.        a)  If you divide tracks into half as many blocks, then you double the read time for a block.…

A processor uses a serial link to communicate with a keyboard for word processing. A typist using this keyboard can type at rates peaking at 120 words per minute, where a word is 6 characters (including spaces and punctuation). The characters will be transmitted from the keyboard in 8-bit ASCII with one stop bit and no parity. Only consider these and no special characters. The programmer writes setup and polling service routines based on a minimum baud rate, but then finds that the keyboard will only interface at 19.2 Kbaud. Will the polling service routine have to change? Why or why not? Baud Rates 300 600 1200 2400 4800 9600 19200

Consider a virtual memory system that can address a total of 32 bytes. You have unlimited hard disk space, but are limited to only 16MB of semiconductor (physical) memory. Assume that virtual and physical pages are each 4 KB in size. What is the total size of the page table in bytes? (Assume that, in addition to the physical page number, each page table entry also contains some status information in the form of a valid bit (V) and a dirty bit (D)).

Let's pretend for a moment that we have a byte-addressable computer with fully associative mapping, 16-bit main memory addresses, and 32 blocks of cache memory. The following holds true if each block is 16 bits in size: a) Determine how many bytes the offset field is. Measure the tag field's width and height in pixels (b).