A swapping system eliminates holes by compaction.Assuming a random distribution of many holes and many data segments and a time to read or write a 32 bit memory word of 14 uses about how long does it take to compact 4 GB. For simplicity assume that word O is part of a hole and that the highest word in memory contains valid data

On the Motorola 68020 microprocessor, a cache access takes two clock cycles. Data access from main memory over the bus to the processor takes three clock cycles in the case of no wait state insertion; the data are delivered to the processor in parallel with delivery to the cache. a. Calculate the effective length of a memory cycle given a hit ratio of 0.9 and a clocking rate of 16.67 MHz. b. Repeat the calculations assuming insertion of two wait states of one cycle each per memory cycle. What conclusion can you draw from the results?

There are many parameters that could be used to describe disk performance; among them are:   number of bits per track disk capacity (in bits) number of disk surfaces rotational speed rotational latency transfer rate tracks per surface sectors per track blocks per track sectors per block seek time speed of disk arm block-read time number of blocks   Some of these parameters are independent, and others are (approximately) linearly related. That is, doubling one doubles the other. Decide which of these parameters are linearly related. Then, select from the list below, the relationship that is true, to within a close approximation. Note: none of the statements may be true exactly, but one will always be much closer to the truth than the other three. Also note: you should assume all dimensions and parameters of the disk are unchanged except for the ones mentioned.        a)  If you divide tracks into half as many blocks, then you double the read time for a block.…

A processor uses a serial link to communicate with a keyboard for word processing. A typist using this keyboard can type at rates peaking at 120 words per minute, where a word is 6 characters (including spaces and punctuation). The characters will be transmitted from the keyboard in 8-bit ASCII with one stop bit and no parity. Only consider these and no special characters. The programmer writes setup and polling service routines based on a minimum baud rate, but then finds that the keyboard will only interface at 19.2 Kbaud. Will the polling service routine have to change? Why or why not? Baud Rates 300 600 1200 2400 4800 9600 19200

A certain disk can read data at a rate of 515.2 MB/s. How many books can be read in 4 seconds if an "average" book has69 pages,20 lines per page,9 words per line,6 characters per word,and each character is one of 100 different characters where the fewest number of bits are used to represent each character?

On the Motorola 68020 microprocessor, a cache access takes two clock cycles. Data access from main memory over the bus to the processor takes three clock cycles in the case of no wait state insertion; the data are delivered to the processor in parallel with delivery to the cache. a. Calculate the effective length of a memory cycle given a hit ratio of 0.9 and a clocking rate of 16.67 MHz. b. Repeat the calculations assuming insertion of two wait states of one cycle each per memory cycle. What conclusion can you draw from the results?

Let's pretend for a moment that we have a byte-addressable computer with fully associative mapping, 16-bit main memory addresses, and 32 blocks of cache memory. The following holds true if each block is 16 bits in size: a) Determine how many bytes the offset field is. Measure the tag field's width and height in pixels (b).