Given in the figure is IC 7474 pin configuration. The pin connections of the IC is provided in the Table for sequence for which it is desined. Intially the FFs states (AB) were reset to 00. 74LS74 Dual D-type Flip Flop D-type Flip-flop Two vcc CLR D CLK PR Q a

QUESTION 12 Flip-flops are normally used for all of the following applications, except logic gates counting frequency division data storage QUESTION 13 Which of the following best describes the action of pulse-triggered flip-flops? The clock and R-S inputs must be pulse shaped. The data is entered on the leading edge of the clock, and transferred out on the trailing edge of the clock. A pulse on the clock transfers data from input to output. The synchronous inputs must be pulsed.

A modulus-8 ring counter requires(a) eight flip-flops (b) four flip-flops(c) five flip-flops (d) twelve flip-flops

In the process of testing a 74LS283 4-bit parallel adder, the following logic levels were observed on its pins: (Please check the datasheet of 74LS283 for more details.) Pin number 1 Logic level HIGH 2 HIGH 3 HIGH 4 HIGH 5 LOW 6 LOW 7 LOW 8 LOW 9 HIGH 10 LOW 11 HIGH 12 LOW 13 HIGH 14 HIGH 15 HIGH HIGH 16 Determine if the IC is functioning properly. If not, what should be the correct logic level at each pin. You need to give as much analysis details as possible.