QUESTION 12 Flip-flops are normally used for all of the following applications, except logic gates counting frequency division data storage QUESTION 13 Which of the following best describes the action of pulse-triggered flip-flops? The clock and R-S inputs must be pulse shaped. The data is entered on the leading edge of the clock, and transferred out on the trailing edge of the clock. A pulse on the clock transfers data from input to output. The synchronous inputs must be pulsed. QUESTION 11 DATA CLK D SRG 4 C QOQ1 Q2 Q3 8783 Figure 8-2 -X Refer to the circuit and waveforms in Figure 8-2. What value is stored in the register at time 'X'? 1110 0110 0111 0101 QUESTION 12 Flip-flops are normally used for all of the following applications, except logic gates counting frequency division data storage

Q1: Design asynchronous counter that counts from 0 to 9 using positive edge- triggered D flip flop. The used flip flop does not have preset and clear inputs. Your answer should include the circuit diagram and the output waveforms.

number 3

Design  a  reverse  counter  with  three  D  flip‐flops  A,  B  and  C.  The counter counts from 7, 6, …, 0, then to 7, and continues.

1. Identify each of these logic gates by name, and complete their respective truth tables Output Output Output B AB Output AB Output AB Output 10 A Output Output A Output AB Output A Output A Output Output Output Output 13 13 AB Outpt ABOutput AB Output 10

Computer Science

Note ID:43901912

Derive the state table and the state diagram of the sequential circuit shown in Fig. P5.8 . Explain the function that the circuit performs.

For the data input and clock in Figure 01 (a), determine the states of each flip-flop in the shift register of Figure 01 (b) and show the Q waveforms. Assume that the register contains all 1s initially. CLK Serial data input (a) FF0 FF1 FF2 FF3 Serial Qo Q1 Q3 Serial data output data D input Serial data output CLK (b) FIGURE 01

(a) Complete the following timing diagram for a J-K flip-flop with a falling-edge trigger and asynchronous ClrN and PreN inputs. ClrN Clock ClrN Clock 2₁ PreN (b) Complete the timing diagram for the following circuit. Note that the Ck inputs on the two flip-flops are different. 2₂ J K ClrN li li CLR Ck D₁ Clock li lz CLR Ck D₂