If a CPU issues a 32-bit address on the address bus, and the computer uses the high-order 12 bits to access the memory map, with the remaining address lines going directly to memory: a) Exactly how many pages of memory does this computer have? b) What is the size of each page?

Computer Architecture (Already submit this question, but I think I got wrong solution) Consider a computer that has a number of registers such that the three registers R0 =1500, R1 = 4500, and R2 = 1000 Show the effective address of memory and the registers’ contents in each of the following instructions 1. ADD (R1), R2 2. MOVE 500(R0), R2 3. ADD (40), R1 4. SUBTRACT (5000), R2 5. ADD #30, R2

Suppose the RAM for a certain computer has 4M words, where each word is 16 bits long. What is the capacity of this memory expressed in bytes? If this RAM is byte addressable, how many bits must an address contain? If this RAM is word addressable, how many bits must an address contain?

Consider a CPU which operates with 20Mbyte/s operating speed. The CPU is operating on program control mode of I/O and it has to transfer data of 20 bytes from it. The data is transferred byte wise. Size of the Status register is 2 bytes. What is the total time needed to perform the data transfer?

The memory size might be specified as follows: Memory Size = Number of Words x The number of bits in a word What is the number of address and data lines necessary to build a 256 X 32 memory circuit utilising a decoder and a multiplexer?

In a computer instruction format, the instruction length is 11 bits and the size of an address field is 4 bits. Is it possible to have 5 two-address instructions 45 one-address instructions 32 zero-address instructions using the specified format? Justify your answer.

Computers designed using the Harvard architecture have two buses: one for data and one for instructions.