Consider the following function. F(x, y.:) =E1.2,5,6} a- Build the truth table of the following function
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Q: 1.2 Show the behaviour of the circuit below using a Truth table
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Q: 1) Construct the truth table for the following expressions: (а) АВ + АB (b) АВ + AВ + АВС
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- - The proportional distribution of A, B, C, D signals is given in the table as a percentage. It “logic 1” when the signals are accepted as active, “logic 0” when they are accepted as passive. takes. - When the proportional sum of active signals is over 50%, its output is "logic1", When we accept "logic 0" when it is below 50%, the output in the table Find the values. - Create an X function based on the logic values you find. Simplify the created X function. - Design the simplified function with NAND and NOR gates. - Set up the circuits you designed with NAND and NOR gates and observe the outputs. Show the output values by drawing a table, applying all possibilities to the input values.- The proportional distribution of A, B, C, D signals is given in the table as a percentage. It “logic 1” when the signals are accepted as active, “logic 0” when they are accepted as passive. takes. - When the proportional sum of active signals is over 50%, its output is "logic1", When we accept "logic 0" when it is below 50%, the output in the table Find the values. - Create an X function based on the logic values you find. Simplify the created X function. - Design the simplified function with NAND and NOR gates.a) Using the K - Map simplify the following standard SOP expression X = Im (0, 1, 3, 4, 5, 6, 9, 11, 12, 14 ) and find the simplified expression for X b) Implement the above simplified expression using gates. C) Write the standard POS expression for X given in part (a), as a function of input variables (A, B, C .) d) Briefiy explain Analog to digital converter ?
- Q1: Design and implement an asynchronous counter that counts from 0000 up to 1100 (modulus 13). Use OR gate, and show in the drawing how the OR gate is connected to truncate the state 1101.Excess-3 code is significant for arithmetic operations as it overcomes shortcoming encountered while using 8421 BCD code to add two decimal digits whose sum exceeds 9. Excess-3 arithmetic uses different algorithm than normal non-biased BCD or binary positional number system. An electronics company has hired your services to design a code converter that converts Binary Coded Decimal (BCD) code for it. Design the converter.Consider a uniform quantizer that uses 3 bits and whose input ranges from -1 V to +1 V. a. How many signal levels are present after the quantizer? b. How large is the quantization step for this quantizer? Provide your answer with 4 significant figures. c. How large is the quantization noise in this quantizer in mW? Provide your answer with 4 significant figures.
- 3-) Analyze the circuits below and write the Boolean equation for each Part. Simplify the equation using Boolean algebra and determine if they function as an XOR, XNOR or neither. A): Dor B): XD XD . DQ#01: The schematic shown in figure below is for Divide_by_11, a frequency divider, that divides clk by 11 and asserts its output for one cycle. The unit consists of a chain toggle-type flip-flops with additional logic to form an output pulse every 11th pulse of clk. The asynchronous signal rst is active-low and drives Q to 1. Develop and verify a model of Divide_by_11. Vcc 20LSB Q2 03MSB clk clk clk clk clk rst rst rst rst wl w2 clk QB cik_by_11 rst rstElectrical Engineering Verilog Design N-bit binary counter which counts the number from 0 to 2N-1. After reaching to maximum count i.e. 2N-1, it again starts the count from 0. i. Write the description of the counter in Verilog ii. Generate the design from the listing ii. Produce the waveforms of the counter
- parity generator design, construct and test a circuit that generates an even parity bit ffrom four messages bits . use XOR gates. adding one more XOR gate, expand the circuit so that it generates an odd parity bit also.A digital circuit's input X (X3,..., Xo) represents a four-bit unsigned number from 0 to 6. The output of the circuit: Y = -X For don't cares, the outputs are set to 0's. Use a multiplexer to implement only the most-significant bit (MSB) of the circuit output. From the list below, select the correct set of multiplexer inputs. Draw (on paper) fully-labeled circuit diagram. (Include complete solution ir the test/exam PDF file). (a) D, 1, 1, D, 0,0, 0,0 (b) D, D, 0,0, 0, 1,0, 1 MacBook AirQ5 (a) Discuss, the major dıfferences between ticld programmable gatc arrays (FPGAS) and programmable logie devices (PLDS. where an FPGA may be approprate in a streamıng TV system. Simple multiplexers can be used to mimic a number of two-input logic functions by appropriate mapping of nputs X X, and SEL Show how the multiplexer shown in figure Q5a can be used to perform the function F= AOB (b) SEL Figure Q5a Figure Q5b (over) shows the schematic of a Xilinx 3000 sennes logic cell M Label the configuration bits of the various multiplexers n the celL with zeroed configuration bits selecting the topmost input to each multuplexer. Each multiplexer has -2 ns, the combinatorial loge block is guaranteed to have WS7 ns, and the D-type flip-flops have t4 ns and r 1 ns (c) We wish to construct a two-bit counter from this logie cell. where Q, and Q are the high and low order outputs of the counter, CLK is the clock signal, AR is an asynchronous reset signal, EN enables the counter, and LD allows…