Assume that you have a CPU that utilizes 5 stages with the following latencies: 1) Fetch (IF) Decode (ID) Execute (ALU) Memory (Mem) 300 ps 400 ps 350 ps 550 ps Write Back (WB) 100 ps Assume that when pipelining each stage costs an extra 20ps for the registers between pipeline stages. a) b) c) For a non-pipelined processor, what is the latency of an instruction? What is the clock rate? For a pipelined processor (5 stages), what is the latency of an instruction? What is the clock rate? If you could split one of the pipeline stages into 2 equal halves, which one would you choose? What would be the new latency and clock rate with this change?

Assume that you have a CPU that utilizes 5 stages with the following latencies: 1) Fetch (IF) Decode (ID) Execute (ALU) Memory (Mem) 300 ps 400 ps 350 ps 550 ps Write Back (WB) 100 ps Assume that when pipelining each stage costs an extra 20ps for the registers between pipeline stages. a) b) c) For a non-pipelined processor, what is the latency of an instruction? What is the clock rate? For a pipelined processor (5 stages), what is the latency of an instruction? What is the clock rate? If you could split one of the pipeline stages into 2 equal halves, which one would you choose? What would be the new latency and clock rate with this change?

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 10RQ: How does pipelining improve CPU efficiency? What’s the potential effect on pipelining’s efficiency...

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Similar questions

If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the fetch cycle is 40% of the processor cycle time, what memory access speed is required to implement load operations with zero wait states and load operations with two wait states?
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The time it takes to perform the fetch instruction and decode instruction steps is called the execution time. True or false?
When an instruction is first fetched from memory, its placed in the _________________ and then ________________to extract its components.
A(n) ____________________ instruction copies data from one memory location to another.
_____ is a CPU design technique in which instruction execution is divided into multiple stages and different instructions can execute in different stages simultaneously.
The 5 stages of a processor have the following latencies: Fetch Decode Execute Memory Write-back 250s 350ps 300ps 500ps 80ps If the processor is non-pipelined: what is the clock cycle time for the processor? What is the latency of an R-type instruction in the processor? If the processor is pipelined: What is the clock cycle time for the processor? What is the latency of an R-type instruction in the processor? If you could split one of the pipeline stages into 2 equal halves, which one would you choose? What is the new clock cycle time? What is the latency of an R-type instruction in the processor?
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Q3: An instruction is stored at location 501 with its address field at location 502. The address field has the value 350. A processor register RI contains the number 150. The index register XR contains the number 200. Evaluate the effective address if the addressing mode of the instruction is: (1) Direct. (2) Immediate. (3) Relative. (4) Register indirect. (5) Indexed address.
True/False Run times of the typical five stages to execute an instruction are as given in some units of time: Instruction Fetch: 10 Instruction Decode: 15 Execute: 30 Memory: 50 Write Back: 20 If this is implemented as a pipelined versus a non-pipelined machine, then depending on the absence of hazards, one could expect the speedup to be about 2.5.