Systems Architecture
7th Edition
ISBN: 9781305080195
Author: Stephen D. Burd
Publisher: Cengage Learning
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Textbook Question
Chapter 4, Problem 8VE
When an instruction is first fetched from memory, it’s placed in the _________________ and then ________________to extract its components.
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The _______________ is a register that holds the address of the next instruction to be executed.
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In the __________ part of the fetch-decode-execute cycle, the CPU determines which operation it should perform. a. fetch b. decode c. execute d. immediately after the instruction is executed
Chapter 4 Solutions
Systems Architecture
Ch. 4 - Prob. 1VECh. 4 - ________________ generates heat in electrical...Ch. 4 - Prob. 3VECh. 4 - Prob. 4VECh. 4 - Prob. 5VECh. 4 - One _________________ is one cycle per second.
Ch. 4 - Prob. 7VECh. 4 - When an instruction is first fetched from memory,...Ch. 4 - Prob. 9VECh. 4 - Prob. 10VE
Ch. 4 - Prob. 11VECh. 4 - Prob. 12VECh. 4 - The contents of a memory location are copied to a...Ch. 4 - Prob. 14VECh. 4 - A(n) ________________ instruction always alters...Ch. 4 - Prob. 16VECh. 4 - A(n) ____________________ instruction copies data...Ch. 4 - The CPU incurs one or more _________________ when...Ch. 4 - The CPU incurs one or more _____ when its idle,...Ch. 4 - In many CPUs, a register called the _____ stores...Ch. 4 - The components of an instruction are its _____ and...Ch. 4 - Two 1-bit values generate a 1 result value when...Ch. 4 - A(n) _____ operation transforms a 0 bit value to 1...Ch. 4 - _____ predicts that transistor density will double...Ch. 4 - A(n) _____ is a measure of CPU or computer system...Ch. 4 - _____ is a CPU design technique in which...Ch. 4 - Describe the operation of a MOVE instruction. Why...Ch. 4 - Prob. 2RQCh. 4 - Prob. 3RQCh. 4 - Prob. 4RQCh. 4 - Prob. 5RQCh. 4 - Prob. 7RQCh. 4 - Prob. 8RQCh. 4 - Prob. 9RQCh. 4 - How does pipelining improve CPU efficiency? What’s...Ch. 4 - Prob. 11RQCh. 4 - Develop a program consisting of primitive CPU...Ch. 4 - If a microprocessor has a cycle time of 0.5...Ch. 4 - Processor R is a 64-bit RISC processor with a 2...Ch. 4 - Prob. 4PECh. 4 - Prob. 1RPCh. 4 - Prob. 2RPCh. 4 - Prob. 3RP
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- 2. Computer designers have invented many variations to the basic form of microcode. For example, the CPU hardware implements the fetch-execute cycle and invokes a microcode procedure for each instruction. What is the advantage and disadvantages of microcode?arrow_forwardWhat is the part of memory address space allocated for a given program responsible to store: a. The program instructions: Instruction register holds each instruction_ b. The data used by the program: and the output is stored by ALU output register_ RAM c. Temporary data:_ _ALU input register 1 and 2 for inputarrow_forwardWhen the INT instruction executes, what is the first task carried out by the CPU?arrow_forward
- The decoded instruction is stored in ______ .arrow_forwardGiven the structure of the CPU in the references section provide the control signals that implements the following instruction. SUB r3, r2, r1arrow_forwardAssume a CPU with a fixed 32-bit instruction length has the following instruction format:opcode mode [operand1] [operand2] [operand3]The mode encodes the number of operands and each operand’s mode. For instance, one mode indicates three registers, another indicates two registers and an immediate datum, another indicates a main memory reference, etc. Assume there are 94 instructions and 22 modes. Answer the following.a. One mode indicates three registers. How many registers can be referenced in this mode?b. One mode indicates two registers and an immediate datum in two’s complement. Assuming there are 32 registers, what is the largest immediate datum that can be referenced?c. One mode has a destination register and a source memory address (an unsignednumber). Assuming 16 registers, what is the largest memory reference available?d. One mode has two memory addresses, both using base displacement. In both, the basesare stored in index registers and the displacements are specified in the…arrow_forward
- In the __________ part of the fetch-decode-execute cycle, the CPU determines which operation it should perform.a. fetchb. decodec. executed. immediately after the instruction is executedarrow_forwardD Question 31 Fill in the blank: LC-3 instruction types include: computational instructions, data movement instructions and __(blank)____. O systematic instructions O conditional instructions O control instructions O reserve instructionsarrow_forwardSTC instruction belongs to _____. a. Direct I/O addressing b. Immediate addressing c. Implied Addressing d. Direct Addressingarrow_forward
- Match the vocabulary below with their correct definitions: the portion of an encoded instruction that tells the CPU what operation to perform a single operation of the CPU a value passed to a function in a high-level language a value that the CPU operates on when executing an instruction 1. Argument 2. Instruction 3. Opcode 4. Operand 5. Parameter 6. Prototypearrow_forwardObjective Learn the basic structure of an assembly program, Data Memory Map how to read the 8-bit instruction setreference and Address Offset Data become familiar with a few commands. Ob00001000 1 Ob10010011 Ob00000101 2 Lab 3 4 Task 1: Walk through the assembly program below and fill out the data memory map (right). If a value changes during the program, you only need to 7 record the final value. Unless otherwise stated all 8. memory locations contain a value of 0. 10 11 12 :Program for task 1 :Definitions 13 14 .EQU myData=0x21 .DEF config=R4 15 Ob10100101 Ob10111001 16 17 :Main 18 .CSEG 19 .ORG Ox0000 20 LDI R16, Ob00001000 MOV RO, R16 21 22 LDI R16, Ob10010011 MOV R1, R16 23 24 LDI R16, Ob01010101 ANDI R16,Ob00001111 25 26 MOV R2, R16 ORI R16, Ob10100101 LDI R17,20 ADD R17, R16 27 28 29 MOV R3, R16 30 MOV config, R17 OUT O, R3 31 32 CBI 0,1 IN R5,0 STS myData, RO SBI 1, 6 SBI 1,7 LDS R6, myData 33 1. 34 2 35 3 36 4 37 5 38 6.arrow_forwardMUL & DIV instruction in Assembly Language Table 1 EAX EBX ECX EDX 10H 20H 2H 0H Refer to Table 1 above for the following tasks.Write your own code in Visual Studio 2019 to execute the instruction, then fill in the blanks with the correct value of the registers. Also, note the changes. **Note: Always start with the initial value of the registers given in Table 1 above for each question (a-f) This means you have to execute only one instruction per debugging session e.g. execute MUL BX and then debug and get the values of the registers and then stop. Then start again with MUL CX. Answer all questions in 32bit format XXXX XXXX e.g. 0000 1000 with only one white space in between a. MUL BX EAX EBX ECX EDX Answer Answer Answer Answer b. MUL CX EAX EBX ECX EDX c. MUL AX EAX EBX ECX EDX d. DIV BX EAX EBX ECX EDX e. DIV CX EAX EBX ECX EDX f. DIV AX…arrow_forward
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